AUX Power Management Control (AUX_CTRL_REG2) – Offset 8154 - 1.3 - ID:767625 | 12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

ID	Date	Version	Classification
767625	07/13/2023		Public

AUX Power Management Control (AUX_CTRL_REG2) – Offset 8154

AUX Power Management Control Register2

Bit Range	Default	Access	Field Name and Description
31	0x1	RW	Disable L1P2 Exit on Wake Enable (DIS_L1P2_EXIT_ON_WAKE_EN) This bit disables the dependency on Wake Enables defined in PORTSC for L1P2 exit when in D0
30	0x0	RW	Link Fast Training Mode (CFG_FAST_TRAINING) 0: Normal operation mode 1: Link fast training mode This bit should be written 0 in normal operation
29	0x0	RW	SNPS PHY Status Done L1 Disable (SNPS_PHYSTATUS_DONE_L1_DIS) SNPS PHY Status Done L1 Disable
28	0x0	RW	Shadow Decode Disable (SHADOW_DECODE_DIS) Shadow Decode Disable
27	0x0	RW	Battery Charge D3 Enable (BATT_CHARGE_D3_EN) Battery Charge D3 Enable
26	0x0	RW	Debounce Enable (CFG_DEBOUNCE_EN) Debounce Enable
25	0x0	RW	PCIe P0 Exit L1 Enable (PCIE_P0_EXIT_L1_EN) PCIe P0 Exit L1 Enable
24	0x1	RW	Enable L1 exit notification to SNPS PCIe core (EN_L1_EXIT_NOTIF_PCIE) This bit enables a L1 exit notification to SNPS PCIe core. There is a case where USB ports have waked up and AUX PM module has started the wakeup process. The AUX PM control state got into a wait for P0 state because it needs to wait until PCIe core to signal powerdown state change. Due to the fact that the core is in D3Hot, there is no run_stop bit set such that no internal interrupt will be fired. This causes the LTSSM of PCIe stayed in L1 even though AUX PM has known that it needs an L1 exit. This bit works together with bit21 of this register. 1: enables this feature 0: disables this feature.
23	0x0	RW	Disable PLC on Disconnect (DIS_PLC_ON_DISCONNECT) 1: do not assert PLC for disconnection 0: assert PLC for disconnection
22	0x0	RW	Treat Idle as TS2 in LTSSM Wait for TS2 (TREAT_IDLE_AS_TS2_IN_LTSSM_WAIT_4_TS2) This bit enables a feature in PCIe core LTSSM to treat IDLE received as TS2 when LTSSM is in wait for TS2 receive state. This is a function requested from PHY where it is possible to not able to receive TS2 without error. 1: treat Logic IDLE as TS2 received when in some PCIe LTSSM state. 0: disable this feature.
21	0x0	RW	Disable p2 overwrite due to the D3HOT where PCIe core enters the L1 (DIS_P2_OVERWRITE_DUE2_D3HOT) This feature applies when if PCIe core LTSSM enters L1 due to the D3hot, the aux PM control will not start a P2 overwrite function in anticipating for the next L23 enter. 1: disables p2 overwrite due to the D3HOT where PCIe core enters the L1. 0: enables P2 overwrite even when in D3Hot state.
20	0x1	RW	Enable the port to enter U3 automatically when in U1/U2 (ENABLE_AUTO_U3_ENTRY_FROM_U2_U3) 1: enables the port to enter U3 automatically when in U1/U2 0: disables the port to enter U3 automatically when in U1/U2
19	0x1	RW	No Linkdown Reset is Issue During Low Power State (DIS_LINKDOWN_RST_DURING_LOW_POWER) No linkdown reset is issue during low power state
18	0x0	RW	Exit Deep Sleep If PCIe In P0 (EN_EXIT_DEEP_SLEEP_IF_PCIE_IN_P0) This bit enables a feature in AUX PM module where if PCIe core LTSSM is in P0 for a duration of time, the controller will exit the deep sleep state. This is for failure control in case. 0: disable this feature 1: enables this feature
17	0x0	RW	U2 Exit LFPS Timer Value (U2_EXIT_LFPS_TIMER_VALUE) This bit selects U2 exit LFPS timer value 0: 320ns 400ns in 25MHz domain 1: 240ns 320ns in 25MHz domain
16	0x1	RW	Enable Exit Deep Sleep on USB Port Wakeup (EN_EXIT_DEEP_SLEEP_ON_USB_PORT_WAKEUP) This bit enables a function that AUX PM module exits from the deep sleep state due to the USB ports wakeup level signal. 0: disables this function which means that a wakeup pulse generated from each USB PortSC event will wake up the AUX PM module from deep sleep if the D3 state is programmed. 1: enables this function
15:14	0x0	RW	P3 Entry Timeout (P3_ENTRY_TIMEOUT) This field defines the timeout value to enter P3 mode in U2. 00: 7us 8us 01: 511us 512us 10: disables the timer (0us) 11: disables the timer (0us)
13	0x1	RW	Enable U2 P3 Mode (EN_U2_P3) 0: Disable U2 P3 mode 1: Enable U2 P3 mode
12:11	0x0	RW	Fine Debug Mode Select (FINE_DM_SEL) Fine Debug Mode Select
10	0x0	RW	Enable Low Power State Based Core Clock Gating (EN_LP_CORE_CG) When set to '1' enable core clock gating based on low power state entered
9	0x1	RW	Disable USB3 Port Status Changed Event (DIS_U3_PORT_SCE) 0: Enable USB3 port status change event generation if any change bit is not cleared 1: Disable USB3 port status change event generation if any change bit is not cleared Bit 12 default 0
8:4	0x0	RW	Debug Mode Select Register (DEB_MODE_SEL) Debug Mode Select Register
3	0x0	RW	Enable Auto Wakeup Non-IDLE (EN_AWAK_NIDLE) When set to 1 enables the auto wakeup function when engine has identified non IDLE condition.
2	0x1	RW	Enable PM Control P1 Exit P2 (EN_PMC_P1_EXIT_P2) When set 1 enables the PM control module to transition to P1 instead of P0 when exit P2.
1	0x1	RW	Enable PCIe PIPE CLK Isolation (EN_PP_CLK_ISOL) When set to 1 enables the PCIe PIPE CLK to be isolated when main power is removed.
0	0x0	RW	Enable P2 Overwrite P1 Allowed Detect (EN_P2OVRP1_ADET) When set to 1 enables a function that can detect whether or not enable P2 overwrite P1 function. The condition to get to P2 overwrite is when engine is in idle conditions. This means that there is no ISO EP pending.