BIOS Reset Complete (BIOS_RESET_CPL_0_0_0_MCHBAR_PCU) – Offset 5DA8 - 1.3 - ID:767625 | 12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

Introduction
Processor Configuration Register Definitions and Address Ranges
D0:F0 Host Bridge and DRAM Controller - DMIBAR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - DMIBAR Registers (part 2)
- DMI VCm Resource Control (DMIVCMRCTL_0_0_0_DMIBAR)
D0:F0 Host Bridge and DRAM Controller - GFXVTBAR Registers
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 1)
- GFX VT Range Base Address Register (GFXVTBAR_0_0_0_MCHBAR_NCU)
- VT DMI PEG VC0 Range Base Address Register (VTDPVC0BAR_0_0_0_MCHBAR_NCU)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 3)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 5)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - PXPEPBAR PCI Express Egress Port Registers
- Egress Port Virtual Channel Control (EPPVCCTL_0_0_0_PXPEPBAR)
- Egress Port Element Declaration Capability (EPESD_0_0_0_PXPEPBAR)
D0:F0 Host Bridge and DRAM Controller - REGBAR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - REGBAR Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR Registers
D1:F0-1 PCI Express* Controller Registers
D10:F0 Platform Monitoring Technology (PMT) Registers
D13:F0 USB Host Controller (xHCI) Registers
D13:F0 USB Host Controller MBAR Registers
D13:F1 USB Device Controller (xDCI) Configuration Registers
D13:F2-3 Thunderbolt DMA Device Registers
D14:F0 Volume Management Device
D14:F0 Volume Management Device MEMBAR2 Registers
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology Registers
D5:F0 Image Processing Unit Registers
D6:F0 PCI Express* Controller Registers (part 1)
D6:F0 PCI Express* Controller Registers (part 2)
- Feature Control 2 (FCTL2)
D7:F0-3 Thunderbolt PCI Express* Controller Registers
D8:F0 Gauss Newton Algorithm Registers

BIOS Reset Complete (BIOS_RESET_CPL_0_0_0_MCHBAR_PCU) – Offset 5DA8

This register is used as interface between BIOS and PCU. It is written by BIOS and read by PCU.

Bit Range	Default	Access	Field Name and Description
31:2	0h	RO	Reserved
1	0x0	RW	PCIe Enumeration Done (PCIE_ENUMERATION_DONE) This will be set after PCIe enumeration is done. This bit will be read by pcode. If it is set, pcode will look at the following register bits: MPVTDTRK_CR_DEVEN_0_0_0_PCI Bit Bit Name 1 D1F2EN 2 D1F1EN 3 D1F0EN If all of these bits are set to a 0x0, this means that there is nothing connected to the PEG devices and the Gen3 PLL can be shut off. Note: Implicit assumption - this bit is asserted prior to (or with) asserting RST_CPL.
0	0x0	RW/1S	Reset Complete (RST_CPL) This bit is set by BIOS to indicate to the CPU Power management function that it has completed to set up all PM relevant configuration and allow CPU Power management function to digest the configuration data and start active PM operation. It is expected that this bit will be set just before BIOS transfer of control to the OS. 0b: Not ready 1b: BIOS PM configuration complete

Bit Range

Default

Access

Field Name and Description

31:2

Reserved

0x0

PCIe Enumeration Done (PCIE_ENUMERATION_DONE)

This will be set after PCIe enumeration is done. This bit will be read by pcode. If it is set, pcode will look at the following register bits:
MPVTDTRK_CR_DEVEN_0_0_0_PCI
Bit Bit Name
1 D1F2EN
2 D1F1EN
3 D1F0EN
If all of these bits are set to a 0x0, this means that there is nothing connected to the PEG devices and the Gen3 PLL can be shut off.
Note: Implicit assumption - this bit is asserted prior to (or with) asserting RST_CPL.

0x0

RW/1S

Reset Complete (RST_CPL)

This bit is set by BIOS to indicate to the CPU Power management function that it has completed to set up all PM relevant configuration and allow CPU Power management function to digest the configuration data and start active PM operation.
It is expected that this bit will be set just before BIOS transfer of control to the OS.
0b: Not ready
1b: BIOS PM configuration complete

Memory Controller BIOS Request (MC_BIOS_REQ_0_0_0_MCHBAR_PCU)

BIOS Mailbox Interface (BIOS_Mailbox_Interface_0_0_0_MCHBAR_PCU) Memory Controller BIOS Request (MC_BIOS_REQ_0_0_0_MCHBAR_PCU)