Capabilities A (CAPID0_A_0_4_0_PCI) – Offset E4 - 1.3 - ID:767625 | 12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

ID	Date	Version	Classification
767625	07/13/2023		Public

Capabilities A (CAPID0_A_0_4_0_PCI) – Offset E4

Processor capability enumeration.

Bit Range	Default	Access	Field Name and Description
31	0x0	RW/L	NVME Device 3 Function 0 Disable (NVME_F0D) 0: Device 3 Function 0 and associated memory spaces are accessible. 1: Device 3 Function 0 (NVMe F0) and associated memory space are disabled by hardwiring the D3F0EN field, bit 5 of the SoC Device Enable register
30	0x0	RW/L	PCIe Device 1 Function 2 Disable (PEG12D) 0: Device 1 Function 2 and associated memory spaces are accessible. 1: Device 1 Function 2 and associated memory and IO spaces are disabled by hardwiring the D1F2EN field, bit 1 of the Device Enable register, (DEVEN Dev 0 Offset 54h) to 0.
29	0x0	RW/L	PCIe Device 1 Function 1 Disable (PEG11D) 0: Device 1 Function 1 and associated memory spaces are accessible. 1: Device 1 Function 1 and associated memory and IO spaces are disabled by hardwiring the D1F1EN field, bit 2 of the Device Enable register, (DEVEN Dev 0 Offset 54h) to 0.
28	0x0	RW/L	PCIe Device 1 Function 0 Disable (PEG10D) 0: Device 1 Function 0 and associated memory spaces are accessible. 1: Device 1 Function 0 and associated memory and IO spaces are disabled by hardwiring the D1F0EN field, bit 3 of the Device Enable register, (DEVEN Dev 0 Offset 54h) to 0.
27	0x0	RW/L	PCIe Link Width Up-config Disable (PELWUD) 0: Link width upconfig is supported. The Processor advertises upconfig capability using the data rate symbol in its TS2 training ordered sets during Configuration.Complete. The CPU responds to link width upconfigs initiated by the downstream device. 1: Link width upconfig is NOT supported. The Processor does not advertise upconfig capability using the data rate field in TS2 training ordered sets during Configuration.Complete. The CPU does not respond to link width upconfigs initiated by the downstream device.
26	0x0	RW/L	DMI Width (DW) 0: DMI x4 1: DMI x2
25	0x0	RW/L	DRAM ECC Disable (ECCDIS) 0: ECC is supported 1: ECC is not supported
24	0x0	RW/L	Force DRAM ECC Enable (FDEE) 0: DRAM ECC optional via software. 1: DRAM ECC enabled. MCHBAR C0MISCCTL bit [0] and C1MISCCTL bit [0] are forced to 1 and Read-Only. Note that FDEE and ECCDIS must not both be set to 1.
23	0x0	RW/L	VT-d Disable (VTDD) 0: VT-d is supported 1: VT-d is not supported
22	0x0	RW/L	DMI GEN2 Disable (DMIG2DIS) 0: Capable of running DMI in Gen 2 mode 1: Not capable of running DMI in Gen 2 mode
21	0h	RO	Reserved
20:19	0x0	RW/L	DRAM Maximum Size per Channel (DDRSZ) This field defines the maximum allowed memory size per channel. 0: Unlimited (64GB per channel) 1: Maximum 8GB per channel 2: Maximum 4GB per channel 3: Maximum 2GB per channel
18	0x0	RW/L	PCIe Controller Device 6 Function 0 Disabled (PEG60D) PCIe Controller Device 6 Function 0 is disabled 0: Device 6 Function 0 is supported 1: Device 6 Function 0 is not supported
17	0x0	RW/L	DRAM 1N Timing Disable (D1NM) 0: Part is capable of supporting 1n mode timings on the DDR interface. 1: Part is not capable of supporting 1n mode. Only supported timings are 2n or greater.
16	0h	RO	Reserved
15	0x0	RW/L	DTT Device Disable (CDD) 0: DTT Device enabled. 1: DTT Device disabled.
14	0x0	RW/L	2 DIMMs Per Channel Enable (DDPCD) Allows Dual Channel operation but only supports 1 DIMM per channel. 0: 2 DIMMs per channel enabled 1: 2 DIMMs per channel disabled. This setting hardwires bits 2 and 3 of the rank population field for each channel to zero. (MCHBAR offset 260h, bits 22-23 for channel 0 and MCHBAR offset 660h, bits 22-23 for channel 1)
13	0x0	RW/L	X2APIC Enable (X2APIC_EN) Extended Interrupt Mode. 0b: Hardware does not support Extended APIC mode. 1b: Hardware supports Extended APIC mode.
12	0x0	RW/L	Dual Memory Channel Support (PDCD) 0: Capable of Dual Channel 1: Not Capable of Dual Channel - only single channel capable.
11	0x0	RW/L	Internal Graphics Disable (IGD) 0: There is a graphics engine within this CPU. Internal Graphics Device (Device 2) is enabled and all of its memory and I/O spaces are accessible. Configuration cycles to Device 2 will be completed within the CPU. All non-SMM memory and IO accesses to VGA will be handled based on Memory and IO enables of Device 2 and IO registers within Device 2 and VGA Enable of the PCI to PCI bridge control register in Devices 1 and 6 (If PCI Express GFX attach is supported). A selected amount of Graphics Memory space is pre-allocated from the main memory based on Graphics Mode Select (GMS in the GGC Register). Graphics Memory is pre-allocated above TSEG Memory. 1: There is no graphics engine within this CPU. Internal Graphics Device (Device 2) and all of its memory and I/O functions are disabled. Configuration cycle targeted to Device 2 will be passed on to DMI. In addition, all clocks to internal graphics logic are turned off. All non-SMM memory and IO accesses to VGA will be handled based on VGA Enable of the PCI to PCI bridge control register in Devices 1 and 6. DEVEN [4:3] (Device 0, offset 54h) have no meaning. Device 2 Functions 0 and 1 are disabled and hidden.
10	0x0	RW/L	DID0 Override Enable (DID0OE) 0: Disable ability to override DID0 - For production 1: Enable ability to override DID - For debug and samples only
9	0h	RO	Reserved
8	0x0	RW/L	2 Level Memory Support (SXP_2LM_SUPPORTED) 0: 2 Level Memory (2LM) is not supported. Only 1LM is supported. 1: 2 Level Memory (2LM) is supported
7:4	0x0	RW/L	Compatibility Revision ID (CRID) Compatibility Revision ID
3	0x0	RW/L	Memory Overclocking (DDR_OVERCLOCK) Memory Overclocking support 0: Memory Overclocking is not supported 1: Memory Overclocking is supported
2	0h	RO	Reserved
1	0x0	RW/L	NVME F7D (NVME_F7D) 0: Device 3 Function 7 and associated memory spaces are accessible. 1: Device 3 Function 7 (NVMe F7) and associated memory space are disabled by hardwiring the D3F7EN field, bit 6 of the SoC Device Enable register
0	0h	RO	Reserved