Capabilities B (CAPID0_B_0_4_0_PCI) – Offset E8 - 1.3 - ID:767625 | 12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

ID	Date	Version	Classification
767625	07/13/2023		Public

Capabilities B (CAPID0_B_0_4_0_PCI) – Offset E8

Processor capability enumeration.

Bit Range	Default	Access	Field Name and Description
31	0x0	RW/L	Image Processing Unit (IPU) Disable (IMGU_DIS) 0: Device 5 associated memory spaces are accessible. 1: Device 5 associated memory and IO spaces are disabled.
30	0x0	RW/L	Trace Hub Disable (NPK_DIS) 0: Trace Hub associated memory spaces are accessible. 1: Trace Hub associated memory and IO spaces are disabled.
29	0x0	RW/L	Overclocking Enabled (OC_ENABLED) 0: Overclocking is Disabled 1: Overclocking is Enabled If overclocking is enabled, MSR FLEX_RATIO.OC_BINS contains how many bits of over-clocking are supported. The encoding is as follows: 0: Overclocking is Disabled 1-6: Turbo ratio limits can be incremented by this amount 7: Unlimited If overclocking is disabled, FLEX_RATIO.OC_BINS is meaningless.
28	0x0	RW/L	SMT Capability (SMT) This setting indicates whether the processor is SMT (HyperThreading) capable.
27:25	0x0	RW/L	Cache Size (CACHESZ) This setting indicates the supporting cache sizes.
24	0x0	RW/L	SVM Disable (SVM_DISABLE) 0: SVM enabled 1: SVM disabled
23:21	0x0	RW/L	Memory 100MHz Reference Clock (PLL_REF100_CFG) DDR Maximum Frequency Capability with 100MHz memory reference clock (ref_clk). 0: 100 MHz memory reference clock is not supported 1-6: Reserved 7: Unlimited
20	0x0	RW/L	PCIe Gen 3 Disable (PEGG3_DIS) 0: Capable of running any of the Gen 3-compliant PCIe controllers in Gen 3 mode (Devices 0/1/x, 0/6/x) 1: Not capable of running any of the PCIe controllers in Gen 3 mode
19	0x0	RW/L	Processor Package Type (PKGTYP) This setting indicates the CPU Package Type.
18:17	0h	RO	Reserved
16	0x0	RW/L	PCIe x16 Disable (PEGX16D) 0: Capable of x16 PCIe Port 1: Not Capable of x16 PCIe port, instead PCIe limited to x8 and below. Causes PCIe port to enable and train logical lanes 7:0 only. Logical lanes 15:8 are powered down (unless in use by the other PEG port or the embedded Display Port), and the Max Link Width field of the Link Capability register reports x8 instead of x16. (In the case of lane reversal, lanes 15:8 are active and lanes 7:0 are powered down.)
15	0x0	RW/L	DMI Gen 3 Disable (DMIG3DIS) DMI Gen 3 Disable
14:12	0x0	RW/L	2 Level Memory Technology Support (LTECH) 0: 1LM 1: EDRAM0 3: EDRAM0+1 4: 2LM Other values are reserved.
11	0x0	RW/L	HDCP Disable (HDCPD) 0: Capable of HDCP 1: HDCP Disabled
10	0x0	RW/L	Device 10 Disable (DEV10_DISABLED) Indicates if Device 10 (Crash Log/Telemetry) is disabled. 0: Device 10 capability is present 1: Device 10 is disabled and locked from further enabling
9	0h	RO	Reserved
8	0x0	RW/L	GNA_DIS (GMM_DIS) GNA (GMM) Disable
7	0x0	RW/L	(DDD) 0: Debug mode 1: Production mode
6:4	0h	RO	Reserved
3	0x0	RW/L	S/H OPI Enable (SH_OPI_EN) Specifies if OPI or DMI are enabled for S/H models. 0: DMI is enabled 1: OPI is enabled
2	0x0	RW/L	VMD Disable (VMD_DIS) Indicates if VMD is disabled.
1	0x0	RW/L	Global Single PCIe Lane (DPEGFX1) This bit has no effect on Device 1 unless Device 1 is configured for at least two ports via PEG0CFGSEL strap. 0: All PCIe port widths do not depend on their respective BCTRL[VGAEN]. 1: Each PCIe port width is limited to x1 operation when its respective BCTRL[VGAEN] is set to 1b.
0	0x0	RW/L	Single PCIe Lane (SPEGFX1) This bit has no effect on Device 1 unless Device 1 is configured for a single port via PEG0CFGSEL strap. 0: Device 1 Function 0 width does not depend on its BCTRL[VGAEN]. 1: Device 1 Function 0 width is limited to x1 operation when its respective BCTRL[VGAEN] is set to 1.