Device Capabilities (DEVICECAP) – Offset 74 - 1.3 - ID:767625 | 12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

Introduction
Processor Configuration Register Definitions and Address Ranges
D0:F0 Host Bridge and DRAM Controller - DMIBAR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - DMIBAR Registers (part 2)
- DMI VCm Resource Control (DMIVCMRCTL_0_0_0_DMIBAR)
D0:F0 Host Bridge and DRAM Controller - GFXVTBAR Registers
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 1)
- GFX VT Range Base Address Register (GFXVTBAR_0_0_0_MCHBAR_NCU)
- VT DMI PEG VC0 Range Base Address Register (VTDPVC0BAR_0_0_0_MCHBAR_NCU)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 3)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 5)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - PXPEPBAR PCI Express Egress Port Registers
- Egress Port Virtual Channel Control (EPPVCCTL_0_0_0_PXPEPBAR)
- Egress Port Element Declaration Capability (EPESD_0_0_0_PXPEPBAR)
D0:F0 Host Bridge and DRAM Controller - REGBAR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - REGBAR Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR Registers
D1:F0-1 PCI Express* Controller Registers
D10:F0 Platform Monitoring Technology (PMT) Registers
D13:F0 USB Host Controller (xHCI) Registers
D13:F0 USB Host Controller MBAR Registers
D13:F1 USB Device Controller (xDCI) Configuration Registers
D13:F2-3 Thunderbolt DMA Device Registers
D14:F0 Volume Management Device
D14:F0 Volume Management Device MEMBAR2 Registers
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology Registers
D5:F0 Image Processing Unit Registers
D6:F0 PCI Express* Controller Registers (part 1)
D6:F0 PCI Express* Controller Registers (part 2)
- Feature Control 2 (FCTL2)
D7:F0-3 Thunderbolt PCI Express* Controller Registers
D8:F0 Gauss Newton Algorithm Registers

Device Capabilities (DEVICECAP) – Offset 74

Capabilities Register

Bit Range	Default	Access	Field Name and Description
31:29	0h	RO	Reserved
28	0x1	RO/V	Functional Level Reset (FLRCAP) A value of 1b indicates the Function supports the optional Function Level Reset mechanism.
27:0	0x8020	RO	Device Capabilities (DEVICECAP) Bits 31:29: Reserved, 0 Bits 27:26: Power Limit Scale: Not applicable, hardwired to 00b Bits 25:18: Power Limit Value: Not applicable, hardwired to 00b Bits 17:16: Reserved, 0. Bit 15: Role-base Error Reporting (RBER): When Set, this bit indicates that the Function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification, Revision 1.0a, and later incorporated into PCI Express Base Specification, Revision 1.1 Bits 14:12: Reserved, 0. Bits 11:9: Endpoint L1 Acceptable Latency: This field indicates the acceptable total latency that an Endpoint can withstand due to the transition from the L1 state to the L0 state. Bits 8:6: Endpoint L0s Acceptable Latency: This field indicates the acceptable total latency that an Endpoint can withstand due to the transition from the L0s state to the L0 state. Bit 5: Extended Tag Field Supported: This bit indicates the maximum supported size of the Tag field as a Requester. Bits 4:3: Phantom Functions Supported: This field indicates the support for use of unclaimed Function Numbers to extend the number of outstanding transactions for PCIe devices. Bits 2:0: Max_Payload_Size Supported: This field indicates the maximum payload size that the Function can support for TLPs. 000b represents 128 bytes, the minimum allowed value.

Bit Range

Default

Access

Field Name and Description

31:29

Reserved

0x1

RO/V

Functional Level Reset (FLRCAP)

A value of 1b indicates the Function supports the optional Function Level Reset mechanism.

27:0

0x8020

Device Capabilities (DEVICECAP)

Bits 31:29: Reserved, 0
Bits 27:26: Power Limit Scale: Not applicable, hardwired to 00b
Bits 25:18: Power Limit Value: Not applicable, hardwired to 00b
Bits 17:16: Reserved, 0.
Bit 15: Role-base Error Reporting (RBER): When Set, this bit indicates that the Function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification, Revision 1.0a, and later incorporated into PCI Express Base Specification, Revision 1.1
Bits 14:12: Reserved, 0.
Bits 11:9: Endpoint L1 Acceptable Latency: This field indicates the acceptable total latency that an Endpoint can withstand due to the transition from the L1 state to the L0 state.
Bits 8:6: Endpoint L0s Acceptable Latency: This field indicates the acceptable total latency that an Endpoint can withstand due to the transition from the L0s state to the L0 state.
Bit 5: Extended Tag Field Supported: This bit indicates the maximum supported size of the Tag field as a Requester.
Bits 4:3: Phantom Functions Supported: This field indicates the support for use of unclaimed Function Numbers to extend the number of outstanding transactions for PCIe devices.
Bits 2:0: Max_Payload_Size Supported: This field indicates the maximum payload size that the Function can support for TLPs. 000b represents 128 bytes, the minimum allowed value.

Device Capabilities and Control (DEVICECTL_DEVICESTS)

PCIe Capabilities (PCIECAPHDR_PCIECAP) Device Capabilities and Control (DEVICECTL_DEVICESTS)