DPC Capability (DPCCAPR) – Offset A04 - 1.3 - ID:767625 | 12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

ID	Date	Version	Classification
767625	07/13/2023		Public

DPC Capability (DPCCAPR) – Offset A04

DPC Capability

Bit Range	Default	Access	Field Name and Description
15:13	0x0	RO	Reserved (RSVD_M) Reserved.
12	0x1	RW/O	DL_Active ERR_COR Signaling Supported (DLAECSS) This field when set, indicates that the Root Port supports the ability to signal with ERR_COR when the link transitions to the DL_Active state. Root Port that supports RP Extensions for DPC must set this bit.
11:8	0x4	RW/O	RP PIO Log Size (RPPIOLS) This field indicates how many DWORDs are allocated for the RP PIO log registers, comprised by the RP PIO Header Log, RP PIO ImpSpec Log and RP PIO TLP Prefix Log. If the Root Port supports RP Extensions for DPC, the value of this field must be 4 or greater - otherwise the value of this field must be 0.
7	0x1	RW/O	DPC Software Triggering Supported (DPCSTS) This field when set, indicates that the Root Port supports the ability for software to trigger DPC. Root Ports that support RP Extensions for DPC must set this bit.
6	0x1	RW/O	Poisoned TLP Egress Blocking Supported (PTLPEBS) This field when set, indicates that the Root Port supports the ability to block the transmission of a poisoned TLP from its Egress port. Root Ports that support RP Extensions for DPC must set this bit.
5	0x1	RW/O	RP Extensions For DPC (RPEFDPC) This field when set, indicates that a Root Port supports a defined set of DPC Extensions that are specific to Root Ports.
4:0	0x0	RW/O	DPC Interrupt Message Number (DPCIMN) This field indicates which MSI/MSI-X vector is used for the interrupt message generated in association with the DPC Capability structure. For MSI, the value in this field indicates the offset between the base Message Data and the interrupt message that is generated. Hardware is required to update this field so that it is correct if the number of MSI Messages assigned to the Function changes when software writes to the Multiple Message Enable field in the MSI Message Control register. For MSI-X, the value in this field indicates which MSI-X Table entry is used to generate the interrupt message. The entry must be one of the first 32 entries even if the Function implements more than 32 entries. For a given MSI-X implementation, the entry must remain constant. If both MSI and MSI-X are implemented, they are permitted to use different vectors, though software is permitted to enable only one mechanism at a time. If MSI-X is enabled, the value in this field must indicate the vector for MSI-X. If MSI is enabled or neither is enabled, the value in this field must indicate the vector for MSI. If software enables both MSI and MSI-X at the same time, the value in this field is undefined. Note: BIOS is expected to update this field with the right value before enabling DPC interrupt.