DPC Status (DPCSR) – Offset A08 - 1.3 - ID:767625 | 12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

ID	Date	Version	Classification
767625	07/13/2023		Public

DPC Status (DPCSR) – Offset A08

DPC Status

Bit Range	Default	Access	Field Name and Description
15:13	0x0	RO	Reserved (RSVD_M) Reserved.
12:8	0x1F	RO/V/P	RP PIO First Error Pointer (RPPIOFEP) The value of this field identifies a bit position in the RP PIO Status register, and this field is considered valid when that bit is set. When this field is valid, and software writes a 1b to the indicated RP PIO Status bit (thus clearing it), this field must revert to its default value. This field is applicable only for Root Ports that support RP Extensions for DPC, and is otherwise reserved. If this field is not reserved, the default value is 11111b.
7	0h	RO	Reserved
6:5	0x0	RO/V/P	DPC Trigger Extension (DPCTE) This field serves as an extension to the DPC Trigger Reason field. When that field is valid and has a value of 11b, this field indicates why DPC has been triggered. 00b: DPC was triggered due to RP PIO error. 01b: DPC was triggered due to DPC Software Trigger bit. 10b: Reserved. 11b: Reserved. This field is valid only when the DPC Trigger Status bit is set and the value of the DPC Trigger Reason field is 11b. Otherwise the value of this field is undefined.
4	0x0	RO/V	DPC RP Busy (DPCRPB) When the DPC Trigger Status bit is Set and this bit is Set, the Root Port is busy with internal activity that must complete before software is permitted to clear the DPC Trigger Status bit. If software Clears the DPC Trigger Status bit while this bit is set, the behavior is undefined. This field is valid only when the DPC Trigger Status bit is Set - otherwise the value of this field is undefined. This bit is applicable only for Root Ports that support RP Extensions for DPC, and is Reserved otherwise.
3	0x0	RW/1C/V/P	DPC Interrupt Status (DPCIS) This bit is set if DPC is triggered while the DPC Interrupt Enable bit is set.
2:1	0x0	RO/V/P	DPC Trigger Reason (DPCTR) This field indicates why DPC has been triggered. 00b: DPC was triggered due to an unmasked uncorrectable error. 01b: DPC was triggered due to receiving an ERR_NONFATAL. 10b: DPC was triggered due to receiving an ERR_FATAL. 11b: DPC was triggered due to a reason that is indicated by the DPC Trigger Reason Extension field. Note: This field is only valid when DPC Trigger Status bit is set - otherwise the value of this field is undefined.
0	0x0	RW/1C/V/P	DPC Trigger Status (DPCTS) When set, indicates that DPC has been triggered. DPC is event triggered. While this bit is set, hardware must direct the LTSSM to the Disabled state. This bit must be cleared before the LTSSM can be released from Disabled state. Once the requirements for how long software must leave the downstream port in DPC is met, software is permitted to clear this bit regardless of the state of other status bits associated with the triggering event. Refer to PCIe Base specification 3.0 for more timing requirements pertaining to this bit.