Error Command (ERRCMD_0_0_0_PCI) – Offset CA - 1.3 - ID:767625 | 12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

ID	Date	Version	Classification
767625	07/13/2023		Public

Error Command (ERRCMD_0_0_0_PCI) – Offset CA

This register controls the Host Bridge responses to various system errors. Since the Host Bridge does not have an SERRB signal, SERR messages are passed from the CPU to the PCH over DMI.
When a bit in this register is set, a SERR message will be generated on DMI whenever the corresponding flag is set in the ERRSTS register. The actual generation of the SERR message is globally enabled for Device #0 via the PCI Command register.

Bit Range	Default	Access	Field Name and Description
15:12	0h	RO	Reserved
11	0x0	RW	MC1 DDR5 CRC Error (MC1_DDR5_CRC) 1: The Host Bridge generates an SERR message over DMI when it detects a CRC error reported by the DRAM controller. 0: Reporting of this condition via SERR messaging is disabled. For systems not supporting DDR5 CRC this bit must be disabled.
10	0x0	RW	MC0 DDR5 CRC Error (MC0_DDR5_CRC) 1: The Host Bridge generates an SERR message over DMI when it detects a CRC error reported by the DRAM controller. 0: Reporting of this condition via SERR messaging is disabled. For systems not supporting DDR5 CRC this bit must be disabled.
9	0x0	RW	Data Uncorrectable Error (MC1_DMERR) 1: The Host Bridge generates an SERR message over DMI when it detects a multiple-bit error reported by the DRAM controller. 0: Reporting of this condition via SERR messaging is disabled. For systems not supporting ECC this bit must be disabled.
8	0x0	RW	Data Single Bit Correctable Error (MC1_DSERR) 1: The Host Bridge generates an SERR special cycle over DMI when the DRAM controller detects a single bit error. 0: Reporting of this condition via SERR messaging is disabled. For systems that do not support ECC this bit must be disabled.
7	0x0	RO	IBECC Uncorrectable Error (IBECC_UC) This bit is deprecated and kept for backwards compatibility. IBECC error messages are logged in the MCA bank.
6	0x0	RO	IBECC Correctable Error (IBECC_COR) This bit is deprecated and kept for backwards compatibility. IBECC error messages are logged in the MCA bank.
5	0x0	RW	SERR on FMHC Unsupported Request Event (FMUR) SERR on FMHC unsupported request event 1: The Host Bridge generates an SERR special cycle over DMI when FMHC reports an unsupported request event. 0: Reporting of this condition via SERR messaging is disabled.
4	0x0	RW	SERR on FMHC CA Event (FMCA) SERR on FMHC CA event 1: The Host Bridge generates an SERR special cycle over DMI when FMHC reports a CA event. 0: Reporting of this condition via SERR messaging is disabled.
3	0x0	RW	SERR on FMI Asynchronous Notification (FMIAN) SERR on FMI Asynchronous Notification error event 1: The Host Bridge generates an SERR special cycle over DMI when FMHC reports a Asynchronous Notification error event with Media dead or Health log critical notification. 0: Reporting of this condition via SERR messaging is disabled.
2	0x0	RW	SERR on FMHC Thermal Event (FMITHERMERR) SERR on FMHC thermal event 1: The Host Bridge generates an SERR special cycle over DMI when FMHC reports a thermal event. 0: Reporting of this condition via SERR messaging is disabled.
1	0x0	RW	Data Uncorrectable Error (MC0_DMERR) 1: The Host Bridge generates an SERR message over DMI when it detects a multiple-bit error reported by the DRAM controller. 0: Reporting of this condition via SERR messaging is disabled. For systems not supporting ECC this bit must be disabled.
0	0x0	RW	Data Single Bit Correctable Error (MC0_DSERR) 1: The Host Bridge generates an SERR special cycle over DMI when the DRAM controller detects a single bit error. 0: Reporting of this condition via SERR messaging is disabled. For systems that do not support ECC this bit must be disabled.