FPB MEM High Vector Control 1 (FPBMEMHVC1) – Offset BB4 - 1.3 - ID:767625 | 12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

ID	Date	Version	Classification
767625	07/13/2023		Public

FPB MEM High Vector Control 1 (FPBMEMHVC1) – Offset BB4

FPB MEM High Vector Control 1

Bit Range	Default	Access	Field Name and Description
31:28	0x0	RW	FPB MEM High Vector Start Lower (FPBMEMHVSL) The value written by software to this field sets the lower bits of the base address at which the FPB MEM High Vector is applied. Software must program this field to a value that is naturally aligned (meaning the lower order bits must be 0s) according to the value in the FPB MEM High Vector Granularity Field as indicated here: FPB MEM High Vector Granularity: Constraint ------------------------------------------------------------ 0000b: <no constraint> 0001b: 0b 0010b: 00b 0011b: 000b 0100b: 0000b 0101b: 0 0000b 0110b: 00 0000b 0111b: 000 0000b If this requirement is violated, the hardware behavior is undefined. If the FPB MEM High Decode Mechanism Supported bit is Clear, then it is permitted for hardware to implement this field as RO, and the value in this field is undefined.
27:8	0h	RO	Reserved
7:4	0x0	RW	FPB MEM High Vector Granularity (FPBMEMHVG) The value written by software to this field controls the granularity of the FPB MEM High Vector, and the required alignment of the FPB MEM High Vector Start Lower field (below). Software is permitted to select any allowed Granularity from the table below regardless of the value in the FPB MEM High Vector Size Supported field. Defined encodings are: Value: Granularity --------------------------- 0000b: 256 MB 0001b: 512 MB 0010b: 1 GB 0011b: 2 GB 0100b: 4 GB 0101b: 8 GB 0110b: 16 GB 0111b: 32 GB All other encodings are Reserved. Based on the implemented FPB MEM High Vector size, hardware is permitted to implement as RW only those bits of this field that can be programmed to non-zero values, in which case the upper order bits are permitted but not required to be hardwired to 0. If the FPB MEM High Decode Mechanism Supported bit is Clear, then it is permitted for hardware to implement this field as RO, and the value in this field is undefined.
3:1	0h	RO	Reserved
0	0x0	RW	FPB MEM High Decode Mechanism Enable (FPBMEMHME) When Set, enables the FPB MEM High Decode mechanism. If the FPB MEM High Decode Mechanism Supported bit is Clear, then it is permitted for hardware to implement this bit as RO, and in this case the value in this field is undefined.