FPB MEM Low Vector Control (FPBMEMLVC) – Offset BB0 - 1.3 - ID:767625 | 12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

ID	Date	Version	Classification
767625	07/13/2023		Public

FPB MEM Low Vector Control (FPBMEMLVC) – Offset BB0

FPB MEM Low Vector Control

Bit Range	Default	Access	Field Name and Description
31:20	0x0	RW	FPB MEM Low Vector Start (FPBMEMLVS) The value written by software to this field sets bits 31:20 of the base address at which the FPB MEM Low Vector is applied. Software must program this field to a value that is naturally aligned (meaning the lower order bits must be 0s) according to the value in the FPB MEM Low Vector Granularity field as indicated here: FPB MEM Low Vector Granularity: Constraint ----------------------------------------------------------------- 0000b: <no constraint> 0001b: 0b 0010b: 00b 0011b: 000b 0100b: 0000b If this requirement is violated, the hardware behavior is undefined. If the FPB MEM Low Decode Mechanism Supported bit is Clear, then it is permitted for hardware to implement this field as RO, and the value in this field is undefined.
19:8	0h	RO	Reserved
7:4	0x0	RW	FPB MEM Low Vector Granularity (FPBMEMLVG) The value written by software to this field controls the granularity of the FPB MEM Low Vector, and the required alignment of the FPB MEM Low Vector Start field (below). Defined encodings are: Value: Granularity --------------------------- 0000b: 1 MB 0001b: 2 MB 0010b: 4 MB 0011b: 8 MB 0100b: 16 MB All other encodings are Reserved. Based on the implemented FPB MEM Low Vector size, hardware is permitted to implement as RW only those bits of this field that can be programmed to non-zero values, in which case the upper order bits are permitted but not required to be hardwired to 0. If the FPB MEM Low Decode Mechanism Supported bit is Clear, then it is permitted for hardware to implement this field as RO, and the value in this field is undefined.
3:1	0h	RO	Reserved
0	0x0	RW	FPB MEM Low Decode Mechanism Enable (FPBMEMLME) When Set, enables the FPB MEM Low Decode mechanism. If the FPB MEM Low Decode Mechanism Supported bit is Clear, then it is permitted for hardware to implement this bit as RO, and in this case the value in this field is undefined.