FPB RID Vector Control 1 (FPBRIDVC1) – Offset BA8 - 1.3 - ID:767625 | 12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

ID	Date	Version	Classification
767625	07/13/2023		Public

FPB RID Vector Control 1 (FPBRIDVC1) – Offset BA8

FPB RID Vector Control 1.

Bit Range	Default	Access	Field Name and Description
31:19	0x0	RW	FPB RID Vector Start (FPBRIDVS) The value written by software to this field controls the offset at which the FPB RID Vector is applied. The value represents a RID offset in units of 8 RIDs, such that bit 0 of the FPB RID Vector represents the range of RIDs starting from the value represented in this register up to that value plus the FPB RID Vector Granularity minus 1, and bit 1 represents range from this register value plus granularity up to that value plus FPB RID Vector Granularity minus 1, etc. Software must program this field to a value that is naturally aligned (meaning the lower order bits must be 0s) according to the value in the FPB RID Vector Granularity Field as indicated here. Encoding (FPB RID Vector Granularity: Start Alignment Constraint): 0000b: <no constraint> 0011b: 00 0b 0101b: 0000 0b All other encodings are Reserved. If this requirement is violated, the hardware behavior is undefined. For Downstream Ports, if the ARI Forwarding Enable bit in the Device Control 2 Register and the FPB RID Decode Mechanism Enable bit are Set, then software must program bits 23:19 of this field to a value of 0000 0b, and the hardware behavior is undefined if any other value is programmed. If the FPB RID Decode Mechanism Supported bit is Clear, then it is permitted for hardware to implement this field as RO, and the value in this field is undefined.
18:8	0h	RO	Reserved
7:4	0x0	RW	FPB RID Vector Granularity (FPBRIDVG) The value written by software to this field controls the granularity of the FPB RID Vector and the required alignment of the FPB RID Vector Start field (below). Granularity encodings: 0000b: 8 RIDs 0011b: 64 RIDs 0101b: 256 RIDs All other encodings are Reserved. Based on the implemented FPB RID Vector size, hardware is permitted to implement as RW only those bits of this field that can be programmed to non-zero values, in which case the upper order bits are permitted but not required to be hardwired to 0. If the FPB RID Decode Mechanism Supported bit is Clear, then it is permitted for hardware to implement this field as RO, and the value in this field is undefined. For Downstream Ports, if the ARI Forwarding Enable bit in the Device Control 2 Register and the FPB RID Decode Mechanism Enable bit are Set, then software must program 0101b into this field, if this field is programmable.
3:1	0h	RO	Reserved
0	0x0	RW	FPB RID Decode Mechanism Enable (FPBRIDME) When Set, enables the FPB RID Decode mechanism. If the FPB RID Decode Mechanism Supported bit is Clear, then it is permitted for hardware to implement this bit as RO, and in this case the value in this field is undefined.