Graphics VTD Base Address LSB (GFXVTDBAR_LSB_0_2_0_PCI) – Offset C8 - 1.3 - ID:767625 | 12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

Introduction
Processor Configuration Register Definitions and Address Ranges
D0:F0 Host Bridge and DRAM Controller - DMIBAR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - DMIBAR Registers (part 2)
- DMI VCm Resource Control (DMIVCMRCTL_0_0_0_DMIBAR)
D0:F0 Host Bridge and DRAM Controller - GFXVTBAR Registers
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 1)
- GFX VT Range Base Address Register (GFXVTBAR_0_0_0_MCHBAR_NCU)
- VT DMI PEG VC0 Range Base Address Register (VTDPVC0BAR_0_0_0_MCHBAR_NCU)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 3)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 5)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - PXPEPBAR PCI Express Egress Port Registers
- Egress Port Virtual Channel Control (EPPVCCTL_0_0_0_PXPEPBAR)
- Egress Port Element Declaration Capability (EPESD_0_0_0_PXPEPBAR)
D0:F0 Host Bridge and DRAM Controller - REGBAR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - REGBAR Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR Registers
D1:F0-1 PCI Express* Controller Registers
D10:F0 Platform Monitoring Technology (PMT) Registers
D13:F0 USB Host Controller (xHCI) Registers
D13:F0 USB Host Controller MBAR Registers
D13:F1 USB Device Controller (xDCI) Configuration Registers
D13:F2-3 Thunderbolt DMA Device Registers
D14:F0 Volume Management Device
D14:F0 Volume Management Device MEMBAR2 Registers
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology Registers
D5:F0 Image Processing Unit Registers
D6:F0 PCI Express* Controller Registers (part 1)
D6:F0 PCI Express* Controller Registers (part 2)
- Feature Control 2 (FCTL2)
D7:F0-3 Thunderbolt PCI Express* Controller Registers
D8:F0 Gauss Newton Algorithm Registers

Graphics VTD Base Address LSB (GFXVTDBAR_LSB_0_2_0_PCI) – Offset C8

This is the base address for the Graphics VTD configuration space.
There is no physical memory within this 4KB window that can be addressed.
The 4KB reserved by this register does not alias to any PCI 2.3 compliant memory mapped space.
On reset, the GFX-VTD configuration space is disabled and must be enabled by writing a 1 to GFXVTDBAREN.
None of the bits in this register are writable in Intel TXT mode.
BIOS programs this register, after which the register cannot be altered.

Bit Range	Default	Access	Field Name and Description
31:12	0x0	RW	GFX-VTD Base Address Lower DWORD (GFXVTDBAR) This field corresponds to bits 31 to 12 of the base address GFX-VTD configuration space. BIOS will program this register resulting in a base address for a 4KB block of contiguous memory address space. This register ensures that a naturally aligned 4KB space is allocated within the first 512GB of addressable memory space. System Software uses this base address to program the GFX-VTD register set.
11:1	0h	RO	Reserved
0	0x0	RW/V	GFX-VTBAR Enable (GFXVTDBAREN) 0: GFX-VTBAR is disabled and does not claim any memory. 1: GFX-VTBAR memory mapped accesses are claimed and decoded appropriately This bit will remain 0 if VTd capability is disabled.

Bit Range

Default

Access

Field Name and Description

31:12

0x0

GFX-VTD Base Address Lower DWORD (GFXVTDBAR)

This field corresponds to bits 31 to 12 of the base address GFX-VTD configuration space.
BIOS will program this register resulting in a base address for a 4KB block of contiguous memory address space.
This register ensures that a naturally aligned 4KB space is allocated within the first 512GB of addressable memory space.
System Software uses this base address to program the GFX-VTD register set.

11:1

Reserved

0x0

RW/V

GFX-VTBAR Enable (GFXVTDBAREN)

0: GFX-VTBAR is disabled and does not claim any memory.
1: GFX-VTBAR memory mapped accesses are claimed and decoded appropriately This bit will remain 0 if VTd capability is disabled.

GFX_VTDBAR_MSB (GFXVTDBAR_MSB_0_2_0_PCI)

Mirror of Base Data of Stolen Memory (BDSM1_0_2_0_PCI) GFX_VTDBAR_MSB (GFXVTDBAR_MSB_0_2_0_PCI)