Link Control (LCTL) – Offset 50 - 1.3 - ID:767625 | 12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

ID	Date	Version	Classification
767625	07/13/2023		Public

Link Control (LCTL) – Offset 50

Link Control

Bit Range	Default	Access	Field Name and Description
15:12	0x0	RO	Reserved (RSVD_M) Reserved.
11	0x0	RW	Link Autonomous Bandwidth Interrupt Enable (LABIE) Link Autonomous Bandwidth Interrupt Enable - When Set, this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been Set.
10	0x0	RW	Link Bandwidth Management Interrupt Enable (LBMIE) When Set, this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been Set. This bit is not applicable and is reserved for Endpoints, PCI Express-to-PCI/PCI-X bridges, and Upstream Ports of Switches. Functions that do not implement the Link Bandwidth Notification Capability must hardwire this bit to 0b. Default value of this bit is 0b.
9	0x0	RW	Hardware Autonomous Width Disable (HAWD) When Set, this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width. Note: When operating as PCI Express, this bit defines the value of the Link Upconfigure Capability in TS2 Ordered Sets. Default value of this bit is 0b.
8	0x0	RO	Enable Clock Power Management (ECPM) Not supported on Root Ports.
7	0x0	RW	Extended Synch (ES) When set, forces extended transmission of FTS ordered sets in FTS and extra TS2 at exit from L1 prior to entering L0.
6	0x0	RW	Common Clock Configuration (CCC) When set, indicates that the Root Port and device are operating with a distributed common reference clock.
5	0x0	WO	Retrain Link (RL) When set, the root port will train its downstream link. This bit always returns '0' when read. Software uses LSTS.LT and LSTS.LTE to check the status of training. It is permitted to write 1b to this bit while simultaneously writing modified values to other fields in this register. If the LTSSM is not already in Recovery or Configuration, the resulting Link training must use the modified values. If the LTSSM is already in Recovery or Configuration, the modified values are not required to affect the Link training that's already in progress.
4	0x0	RW	Link Disable (LD) When set, the root port will disable the link by directing the LTSSM to the Disabled state.
3	0x0	RW/O	Read Completion Boundary Control (RCBC) Indicates the read completion boundary is 64 bytes.
2	0h	RO	Reserved
1:0	0x0	RW	Active State Link PM Control (ASPM) Indicates whether the root port should enter L0s or L1 or both. Bits Definition 00 Disabled 01 L0s Entry Enabled 10 L1 Entry Enabled 11 L0s and L1 Entry Enabled The value of this register is used unless the Root Port ASPM Control Override Enable register is set, in which case the Root Port ASPM Control Override value is used. Note: If STRPFUSECFG.ASPMDIS is '1', hardware will always see '00' as an output from this register. BIOS reading this register should always return the correct value.