Link Status (LSTS) – Offset 52 - 1.3 - ID:767625 | 12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

ID	Date	Version	Classification
767625	07/13/2023		Public

Link Status (LSTS) – Offset 52

Link Status

Bit Range	Default	Access	Field Name and Description
15	0x0	RW/1C/V	Link Autonomous Bandwidth Status (LABS) This bit is Set by hardware to indicate that hardware has autonomously changed Link speed or width, without the Port transitioning through DL_Down status, for reasons other than to attempt to correct unreliable Link operation. This bit must be set if the Physical Layer reports a speed or width change was initiated by the Downstream component that was indicated as an autonomous change. The default value of this bit is 0b.
14	0x0	RW/1C/V	Link Bandwidth Management Status (LBMS) This bit is Set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: A Link retraining has completed following a write of 1b to the Retrain Link bit Note: This bit is Set following any write of 1b to the Retrain Link bit, including when the Link is in the process of retraining for some other reason. Hardware has changed Link speed or width to attempt to correct unreliable Link operation, either through an LTSSM timeout or a higher level process This bit must be set if the Physical Layer reports a speed or width change was initiated by the Downstream component that was not indicated as an autonomous change. The default value of this bit is 0b.
13	0x0	RO/V	Link Active (LA) Set to 1b when the Data Link Control and Management State Machine is in the DL_Active state, 0b otherwise.
12	0x1	RO/V	Slot Clock Configuration (SCC) In normal mode, Root Port uses the same reference clock as on the platform and does not generate its own clock. Note: When operating in PCI Express mode, the default of this register bit is dependent on the 'PCIe Non-Common Clock With SSC Mode Enable Strap'. If the strap enables non-common clock with SSC support, this bit shall default to '0'. Otherwise, this bit shall default to '1'.
11	0x0	RO/V	Link Training (LT) The root port sets this bit whenever link training is occurring, or that 1b was written to the Retrain Link bit but Link training has not yet begun. It clears the bit upon completion of link training.
10	0h	RO	Reserved
9:4	0x1	RO/V	Negotiated Link Width (NLW) Negotiated link width. 0x1: x1 Link Width 0x2: x2 Link Width 0x4: x4 Link Width 0x8: x8 Link Width 0x10: x16 Link Width The value of this register is undefined if the link has not successfully trained.
3:0	0x1	RO/V	Current Link Speed (CLS) This field indicates the negotiated Link speed of the given link. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the current Link speed. Defined encodings are: '0001b': Supported Link Speeds Vector field bit 0. '0010b': Supported Link Speeds Vector field bit 1. '0011b': Supported Link Speeds Vector field bit 2. '0100b': Supported Link Speeds Vector field bit 3. '0101b': Supported Link Speeds Vector field bit 4. '0110b': Supported Link Speeds Vector field bit 5. '0111b': Supported Link Speeds Vector field bit 6. All other encodings are reserved. The value of this field is undefined if the link is not up. Register Attribute: Static.