Memory Controller BIOS Data (MC_BIOS_DATA_0_0_0_MCHBAR_PCU) – Offset 5E04 - 1.3 - ID:767625 | 12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

ID	Date	Version	Classification
767625	07/13/2023		Public

Memory Controller BIOS Data (MC_BIOS_DATA_0_0_0_MCHBAR_PCU) – Offset 5E04

Memory Controller Frequency information for BIOS, during MRC flow.
Reflects the last frequency requested in MC_BIOS_REQ_0_0_0_MCHBAR_PCU.
In case of Dual MRC for System Agent SpeedStep, the value will change according to the MRC requests.
Post MRC will hold the last MRC request and not the current memory frequency.

Bit Range	Default	Access	Field Name and Description
31	0h	RO	Reserved
30:27	0x0	RW	Request VDDQ TX IccMax (VDDQ_TX_ICCMAX) Peak current on VDDQTX rail at this clock frequency and gear configuration. Described in 0.25A resolution. Max: 32 * 0.25 = 8A;
26:17	0x0	RW	Request VDDQ TX Voltage (VDDQ_TX_VOLTAGE) Voltage of the VDDQTX rail at this clock frequency and gear configuration. Described in 5mV resolution.
16:14	0h	RO	Reserved
13:12	0x0	RW/L	Gear Type (GEAR) 0: Gear1 (Default) - DDR bus clock is the same as QCLK 1: Gear2 - DDR PHY bus clock is double of QCLK 2: Gear4 - DDR PHY bus clock is quad of QCLK
11:8	0x0	RW/L	Reference Clock Type (MC_PLL_REF) This field holds the memory controller frequency Type. 0: MC frequency request for 133MHz Qclk granularity. 1: MC frequency request for 100MHz Qclk granularity. All other values are reserved.
7:0	0x0	RW/L	MC PLL Ratio (MC_PLL_RATIO) This field holds the memory controller frequency (QCLK). Each bin is 133/100MHz and not 266/200MHz. This interface replaces the usage of DCLK ratios and Odd Ratio. QCLK frequency is determined by the MC reference clock (MC_FREQ_TYPE) as well as BCLK. Binary Dec DCLK Equation DCLK Freq QCLK Equation QCLK Freq 0000b 0d ------------------------------------ MC PLL - shutdown -------------------------------------------- ... 0011b 3d 3 * 66.66 200.00 MHz 3 * 133.33 400.00 MHz 0100b 4d 4 * 66.66 266.66 MHz 4 * 133.33 533.33 MHz 0101b 5d 5 * 66.66 333.33 MHz 5 * 133.33 666.67 MHz 0110b 6d 6 * 66.66 400.00 MHz 6 * 133.33 800.00 MHz 0111b 7d 7 * 66.66 466.66 MHz 7 * 133.33 933.33 MHz 1000b 8d 8 * 66.66 533.33 MHz 8 * 133.33 1066.67 MHz ... The values above are given in units of 133.33MHz (400/3). A value of zero implies that the memory controller PLL is shut down.