12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2
ID | Date | Version | Classification |
---|---|---|---|
767625 | 07/13/2023 | Public |
Memory Controller BIOS Request (MC_BIOS_REQ_0_0_0_MCHBAR_PCU) – Offset 5E00
This register allows BIOS to request Memory Controller clock frequency.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0x0 | RW | RUN/BUSY Bit (RUN_BUSY) This bit indicates that the BIOS request is pending. |
30:27 | 0x0 | RW | Request VDDQ TX IccMax (REQ_VDDQ_TX_ICCMAX) Peak current on VDDQTX rail at this clock frequency and gear configuration. Described in 0.25A resolution. Max: 32 * 0.25 = 8A; |
26:17 | 0x0 | RW | Request VDDQ TX Voltage (REQ_VDDQ_TX_VOLTAGE) Voltage of the VDDQTX rail at this clock frequency and gear configuration. Described in 5mV resolution. |
16:14 | 0h | RO | Reserved |
13:12 | 0x0 | RW | Gear Type (GEAR) 0: Gear1 (Default) - DDR bus clock is the same as QCLK |
11:8 | 0x0 | RW | Reference Clock Type (MC_PLL_REF) Request Type: |
7:0 | 0x0 | RW | MC PLL Ratio (MC_PLL_RATIO) This field holds the memory controller frequency request (QCLK). Each bin is 133/100MHz and not 266/200MHz. |