Physical Layer 32.0 GT/s Status (G5STS) – Offset AE8 - 1.3 - ID:767625 | 12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

ID	Date	Version	Classification
767625	07/13/2023		Public

Physical Layer 32.0 GT/s Status (G5STS) – Offset AE8

Physical Layer 32.0 GT/s Status

Bit Range	Default	Access	Field Name and Description
31:11	0x0	RO	Reserved (RSVD_M) Reserved
10	0x0	RO/V	No Equalization Needed Received (NOEQR) When Set, this Port either received a Modified TS1/TS2 with the No Equalization Needed bit Set or received a non-modified TS1/TS2 was recieved with the No Equalization Needed encoding (also reported in the Received Enhanced Link Behavior Control field). Default is 0b.
9	0x0	RO/V	Transmitter Precode Request (TXPRECODER) When Set, this Port will request the transmitter to use Precoding by setting the Precoding Request bit in the TS1s/TS2s it transmits prior to entry to Recovery.Speed Default is Implementation Specific.
8	0x0	RO/V	Transmitter Precoding On (TXPRECODEO) This field indicates whether the Receiver asked this transmitter to enable Precoding. This bit is cleared on DL_Down.
7:6	0x0	RO/V	Received Enhanced Link Behavior Control (RCVDELBCTL) This field contains the Enhanced Link Behavior Control bits from the most recent TS1 or TS2 received in the Polling or Configuration states. This field is Cleared on DL_Down.
5	0x0	RO/V	Modified TS Received (MODTSRCVD) If Set, Received Modified TS Data 1 Register and Received Modified TS Data 2 Register contain meaningful data. This bit is Cleared when the Link is Down. This bit is Set when the Modified TS1/TS2 Ordered Set is received
4	0x0	RW/1C/V/P	Link Equalization Request 32.0 GT/s (LERG5) This bit is Set by hardware to request the 32.0 GT/s Link equalization process to be performed on the Link. For a Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions.
3	0x0	RO/V/P	Equalization 32.0 GT/s Phase 3 Successfu (EQ32PH3SUCC) When set to 1b, this bit indicates that Phase 3 of the 32.0 GT/s Transmitter Equalization procedure has successfully completed. For a Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions.
2	0x0	RO/V/P	Equalization 32.0 GT/s Phase 2 Successful (EQ32PH2SUCC) When set to 1b, this bit indicates that Phase 2 of the 32.0 GT/s Transmitter Equalization procedure has successfully completed. For a Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions.
1	0x0	RO/V/P	Equalization 32.0 GT/s Phase 1 Successful (EQ32PH1SUCC) When set to 1b, this bit indicates that Phase 1 of the 32.0 GT/s Transmitter Equalization procedure has successfully completed. he default value of this bit is 0b. For a Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions.
0	0x0	RO/V/P	Equalization 32.0 GT/s Complete (EQ32CMPLT) When Set, this bit indicates that the 32.0 GT/s Transmitter Equalization procedure has completed. For a Multi-Function Upstream Port, this bit must be implemented in Function 0 and RsvdZ in other Functions.