Power Management Control Status (PM_CONTROL_STATUS) – Offset D4 - 1.3 - ID:767625 | 12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

ID	Date	Version	Classification
767625	07/13/2023		Public

Power Management Control Status (PM_CONTROL_STATUS) – Offset D4

The Data register is an optional, 8-bit read-only register that provides a mechanism for the function to report state dependent operating data such as power consumed or heat dissipation. Typically the data returned through the Data register is a static copy (look up table, for example) of the function's worst case 'DC characteristics' data sheet. This data, when made available to system software, could then be used to intelligently make decisions about power budgeting, cooling requirements, etc.

Bit Range	Default	Access	Field Name and Description
31:24	0x0	RO	(DATA) The data register, data scale and data select registers are not supported. Hardwired to zero.
23:16	0h	RO	Reserved
15	0x0	RO	PME# Status (PME_STATUS) This bit is set when the function would normally assert the PME# signal independent of the state of the PME_En bit. This bit is hardwired to 0b to indicate that PME# assertion from D3 (cold) is not supported.
14:13	0x0	RO	Data Scale (DATA_SCALE) The data register, data scale and data select registers are not supported.
12:9	0x0	RO	Data Select (DATA_SELECT) The data register, data scale and data select registers are not supported.
8	0x0	RO	PME Enable (PME_ENABLE) This bit is hardwired to 0b to indicate that PME# assertion from D3 (cold) is disabled.
7:4	0h	RO	Reserved
3	0x1	RO	No Soft Reset (NO_SOFT_RESET) When set to 1 this bit indicates that the device is transitioning from D3hot to D0 because the power state commands do not perform a internal reset. Config context is preserved. Upon transition no additional operating system intervention is required to preserve configuration context beyond writing the power state bits. When clear the devices do not perform an internal reset upon transitioning from D3hot to D0 via software control of the power state bits. Regardless of this bit the devices that transition from a D3hot to D0 by a system or bus segment reset will return to the device state D0 uninitialized with only PME context preserved if PME is supported and enabled.
2	0h	RO	Reserved
1:0	0x0	RW	Power State (POWER_STATE) This field indicates the current power state of the device and can be used to set the device into a new power state. If software attempts to write an unsupported state to this field, the write operation must complete normally on the bus, but the data is discarded and no state change occurs.