Protected Audio Video Path Control (PAVPC_0_0_0_PCI) – Offset 58 - 1.3 - ID:767625 | 12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

ID	Date	Version	Classification
767625	07/13/2023		Public

Protected Audio Video Path Control (PAVPC_0_0_0_PCI) – Offset 58

All the bits in this register are locked by Intel TXT. When locked the R/W bits are RO.

Bit Range	Default	Access	Field Name and Description
31:20	0x0	RW/L	(PCMBASE) Sizes supported: 1M, 2M, 4M and 8M. Base value programmed (from Top of Stolen Memory) itself defines the size of the WOPCM. Separate WOPCM size programming is redundant information and not required. Default 1M size programming. 4M recommended. This register is locked (becomes read-only) when PAVPE = 1b.
19:7	0h	RO	Reserved
6	0x0	RW/L	(ASMFEN) ASMF method enabled 0b Disabled (default). 1b Enabled. This register is locked when PAVPLCK is set.
5	0h	RO	Reserved
4	0x0	RW/L	(OVTATTACK) Override of Unsolicited Connection State Attack and Terminate. 0: Disable Override. Attack Terminate allowed. 1: Enable Override. Attack Terminate disallowed. This register bit is locked when PAVPE is set.
3	0x0	RW/L	(HVYMODSEL) This bit is applicable only for PAVP2 operation modePAVP3 mode, this one type boot time programming has been replaced by per-App programming (through the Media Crypto Copy command). Note that PAVP2 or PAVP3 mode selection is done by programming bit 8 of the MFX_MODE - Video Mode register.
2	0x0	RW/L	(PAVPLCK) This bit locks all writable contents in this register when set (including itself). Only a hardware reset can unlock the register again. This lock bit needs to be set only if PAVP is enabled (bit 1 of this register is asserted).
1	0x0	RW/L	(PAVPE) 0: PAVP functionality is disabled. 1: PAVP functionality is enabled. This register is locked when PAVPLCK is set.
0	0x1	RW/L	(PCME) This field enables Protected Content Memory within Graphics Stolen Memory. This memory is the same as the WOPCM area, whose size is defined by bit 5 of this register. This register is locked when PAVPLOCK is set. A value of 0 in this field indicates that Protected Content Memory is disabled, and cannot be programmed in this manner when PAVP is enabled. A value of 1 in this field indicates that Protected Content Memory is enabled, and is the only programming option available when PAVP is enabled. For non-PAVP3 Mode, even for Lite mode configuration, this bit should be programmed to 1 and HVYMODESEL = 0). This bit should always be programmed to 1 if bits 1 and 2 (PAVPE and PAVP lock bits) are both set. With per-application Memory configuration support, the range check for the WOPCM memory area should always happen when this bit is set, regardless of Lite mode, Serpent mode, PAVP2 or PAVP3 mode programming.