SC ODT MATRIX 0 0 0 MCHBAR (SC_ODT_MATRIX_0_0_0_MCHBAR) – Offset E080 - 1.3 - ID:767625 | 12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

ID	Date	Version	Classification
767625	07/13/2023		Public

SC ODT MATRIX 0 0 0 MCHBAR (SC_ODT_MATRIX_0_0_0_MCHBAR) – Offset E080

ODT matrix (enabled using SC_GS_CFG_0_0_0_MCHBAR.enable_odt_matrix
Note: In DDR5 this matrix should only be used for non target ODT (target ODT should not be specified in this register)

Bit Range	Default	Access	Field Name and Description
31:28	0x0	RW	Write Rank 3 (Write_Rank_3) Indicate which ranks should terminate when writing to rank 3 (bits 3:0 correspond to ODT pins 3:0.) Note: In DDR5 this register should only be used for non target ODT (target ODT should not be specified in this register)
27:24	0x0	RW	Write Rank 2 (Write_Rank_2) Indicate which ranks should terminate when writing to rank 2 (bits 3:0 correspond to ODT pins 3:0). Note: In DDR5 this register should only be used for non target ODT (target ODT should not be specified in this register)
23:20	0x0	RW	Write Rank 1 (Write_Rank_1) Indicate which ranks should terminate when writing to rank 1 (bits 3:0 correspond to ODT pins 3:0). Note: In DDR5 this register should only be used for non target ODT (target ODT should not be specified in this register)
19:16	0x0	RW	Write Rank 0 (Write_Rank_0) Indicate which ranks should terminate when writing to rank 0 (bits 3:0 correspond to ODT pins 3:0), Note: In DDR5 this register should only be used for non target ODT
15:12	0x0	RW	Read Rank 3 (Read_Rank_3) Indicate which ranks should terminate when reading from rank 3 (bits 3:0 correspond to ODT pins 3:0) Note that according to DRAM spec the target rank should not be terminated.
11:8	0x0	RW	Read Rank 2 (Read_Rank_2) Indicate which ranks should terminate when reading from rank 2 (bits 3:0 correspond to ODT pins 3:0) Note that according to DRAM spec the target rank should not be terminated.
7:4	0x0	RW	Read Rank 1 (Read_Rank_1) Indicate which ranks should terminate when reading from rank 1 (bits 3:0 correspond to ODT pins 3:0) Note that according to DRAM spec the target rank should not be terminated.
3:0	0x0	RW	Read Rank 0 (Read_Rank_0) Indicate which ranks should terminate when reading from rank 0 (bits 3:0 correspond to ODT pins 3:0) Note that according to DRAM spec the target rank should not be terminated.