Scheduler Configuration (SC_GS_CFG_0_0_0_MCHBAR) – Offset E088 - 1.3 - ID:767625 | 12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

ID	Date	Version	Classification
767625	07/13/2023		Public

Scheduler Configuration (SC_GS_CFG_0_0_0_MCHBAR) – Offset E088

This register is used for Scheduler configuration

Bit Range	Default	Access	Field Name and Description
63:61	0h	RO	Reserved
60:56	0x1	RW	tCPDED Timing Parameter (tCPDED) Holds DDR timing parameter tCPDED. Power down to command bus tri-state delay in tCK cycles (for DDR4 only) Supported range is 0-7 in 1N mode.
55	0h	RO	Reserved
54	0x0	RW	WCK Differential Low In Idle (WCKDiffLowInIdle) PHY holds WCK to a differential value instead of turning it off. This register is a shadow copy of the DDRPHY register and should match the factory default value of the DDRPHY register
53:50	0h	RO	Reserved
49	0x0	RW	Enable Write Zero (write0_enable) Enable write0 for power saving. This bit should only be set in normal mode.
48:34	0h	RO	Reserved
33:32	0x0	RW	1 DIMM Per Channel Split Ranks on Sub-channel (ddr_1dpc_split_ranks_on_subch) Performance optimization for 1 DIMM Per Channel (1DPC) with dual rank. To be used only with Intel Memory reference Code as there are couple of low level configurations to enable it. For DDR5: the only legal configuration is 0x1,0x2. This CR can never be set to '0 for DDR5
31	0x0	RW	Gear2 Mode (gear2) Indicate that MC is working in Gear-2 (Qclk is half the data transfer clock of the DRAM)
30	0x0	RW	No Gear2 Param Divide (no_gear2_param_divide) Don't do RU[param/2] for DRAM timing parameters when in gear-2, treat the value given in them in DCLKs instead of tCK clocks. For extending the existing ranges (mainly for Overclocking).
29:28	0x0	RW	x8 Device (x8_device) DIMM is made out of X8 devices LSB is for DIMM 0, MSB is for DIMM 1. For DDR5 1DPC, configure this option the same for both sub channels.
27:17	0h	RO	Reserved
16	0x0	RW	No Gear4 Parameter Divide (no_gear4_param_divide) Don't do RU[param/4] for DRAM timing paramters when in Gear4, divide only by 2 (RU[param/2]). This enables a wider parameter range.
15	0x0	RW	Gear4 Mode (gear4) Indicate that MC is working in Gear4 (Qclk is quarter the data transfer clock of the DRAM)
14:12	0h	RO	Reserved
11:8	0x0	RW	Address Mirror (Address_mirror) DIMM routing causes address mirroring For DDR4: bit 0: DIMM 0 (rank 1 bus is mirrored) bit 1: DIMM 1 (rank 3 bus is mirrored) For DDR5 bit 0: Rank0 on Dimm0 is mirrored bit 1: Rank1 on Dimm0 is mirrored bit 2: Rank0 on Dimm1 is mirrored (Rank 2) bit 3: Rank1 on Dimm1 is mirrored (Rank 3) For LPDDR4 bit 0: Sub channel 0 ranks 0 and 2 CA bus is mirrored. bit 1: Sub channel 1 ranks 0 and 2 CA bus is mirrored. bit 2: Sub channel 0 ranks 1 and 3 CA bus is mirrored. bit 3: Sub channel 1 ranks 1 and 3 CA bus is mirrored.
7:5	0x1	RW	N to 1 Ratio (N_to_1_ratio) When using N:1 command stretch mode, every how many B2B valid command cycles a bubble is required Supported range is 1 to 7
4:3	0x0	RW	CMD Stretch (CMD_stretch) Command stretch mode: 00b: 1N 01b: 2N 10b: 3N 11b: N:1 Notice that in Gear2 MC uses only the low phase of Dclk for commands, effectively doing a 2N by default. setting 2N in Gear2 will result in 4N at DDR interface
2:0	0h	RO	Reserved