Slot Control (SLCTL) – Offset 58 - 1.3 - ID:767625 | 12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

ID	Date	Version	Classification
767625	07/13/2023		Public

Slot Control (SLCTL) – Offset 58

Slot Control

Bit Range	Default	Access	Field Name and Description
15:14	0x0	RO	Reserved (RSVD_M) Reserved.
13	0x0	RW	Auto Slot Power Limit Disable (ASPLD) When set, this bit disables automatic sending of Set_Slot_Power_Limit message when the link transitions from non-DL_Up status to DL_Up status.
12	0x0	RW	Data Link Layer State Changed Enable (DLLSCE) When set, this field enables generation of a hot plug interrupt when the Data Link Layer Link Active field is changed.
11	0x0	RW	Electromechanical Interlock Control (EMIC) When software writes either a 1 to this bit, The PCIe port pulses the EMIL pin per PCIExpress Server/Workstation Module Electromechanical Spec Rev 1.0. Write of 0 has no effect. This bit always returns a 0 when read. If electromechanical lock is not implemented, then either a write of 1 or 0 to this register has no effect.
10	0x0	RW	Power Controller Control (PCC) This bit indicates the current state of the Power applied to the slot of the PCI Express port. Reads of this field must reflect the value from the latest write, even if the corresponding hot-plug command is not executed yet at the VPP, unless software issues a write without waiting for the previous command to complete in which case the read value is undefined. 0: Power On 1: Power Off
9:8	0x0	RW	Power Indicator Control (PIC) If a Power Indicator is implemented, writes to this register set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write, even if the corresponding hot-plug command is not executed yet at the VPP, unless software issues a write without waiting for the previous command to complete in which case the read value is undefined. 00: Reserved. 01: On 10: Blink (The PCIe cluster drives 1.5 Hz square wave for Chassis mounted LEDs in the case of legacy card form factor for PCI-Express devices) 11: Off When this register is written, the event is signaled via the virtual pins of the switch over the SMBus port. The switch does not generated the Power_Indicator_On/Off/Blink messages on PCI Express when this field is written to by software.
7:6	0x0	RW	Attention Indicator Control (AIC) If an Attention Indicator is implemented, writes to this register sets the Attention Indicator to the written state. Reads of this field reflect the value from the latest write, even if the corresponding hot-plug command is not executed yet at the VPP, unless software issues a write without waiting for the previous command to complete in which case the read value is undefined. 00: Reserved. 01: On 10: Blink (The switch drives 1.5 Hz square wave) 11: Off When this register is written, the event is signaled via the virtual pins of the switch over the SMBus port.
5	0x0	RW	Hot Plug Interrupt Enable (HPE) When set, enables generation of a hot plug interrupt on enabled hot plug events.
4	0x0	RW	Command Completed Interrupt Enable (CCE) This field enables the generation of Hot-plug interrupts when a command is completed by the Hot-plug controller connected to the PCI-Express port. 0: Disables hot-plug interrupts on a command completion by a hot-plug Controller 1: Enables hot-plug interrupts on a command completion by a hot-plug Controller
3	0x0	RW	Presence Detect Changed Enable (PDE) When set, enables the generation of a hot plug interrupt or wake message when the presence detect logic changes state.
2	0x0	RW	MRL Sensor Changed Enable (MSE) This bit enables the generation of hot-plug interrupts or wake messages via a MRL Sensor changed event. 0: Disables generation of hot-plug interrupts or wake messages when an MRL Sensor changed event happens. 1: Enables generation of hot-plug interrupts or wake messages when an MRL Sensor changed event happens.
1	0x0	RW	Power Fault Detected Enable (PFE) This bit enables the generation of hot-plug interrupts or wake messages via a power fault event. 0: Disables generation of hot-plug interrupts or wake messages when a power fault event happens. 1: Enables generation of hot-plug interrupts or wake messages when a power fault event happens.
0	0x0	RW	Attention Button Pressed Enable (ABE) This bit enables the generation of hot-plug interrupts or wake messages via an attention button pressed event. 0: Disables generation of hot-plug interrupts or wake messages when the attention button is pressed. 1: Enables generation of hot-plug interrupts or wake messages when the attention button is pressed