Slot Status (SLSTS) – Offset 5A - 1.3 - ID:767625 | 12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

ID	Date	Version	Classification
767625	07/13/2023		Public

Slot Status (SLSTS) – Offset 5A

Slot Status

Bit Range	Default	Access	Field Name and Description
15:9	0x0	RO	Reserved (RSVD_M) Reserved.
8	0x0	RW/1C/V	Data Link Layer State Changed (DLLSC) This bit is set when the value reported in Data Link Layer Link Active field of the Link Status register is changed. In response to a Data Link Layer State Changed event, software must read Data Link Layer Link Active field of the Link Status register to determine if the link is active before initiating configuration cycles to the hot plugged device.
7	0x0	RO/V	Electromechanical Interlock Status (EMIS) A read to this register returns the current state of the Electromechanical Interlock (the EMILS pin) which has the defined encodings as: 0: Electromechanical Interlock Disengaged 1: Electromechanical Interlock Engaged
6	0x0	RO/V	Presence Detect State (PDS) If XCAP.SI is set (indicating that this root port spawns a slot), then this bit indicates whether a device is connected (1) or empty (0). If XCAP.SI is cleared, this bit is a 1.
5	0x0	RO/V	MRL Sensor State (MS) This bit reports the status of an MRL sensor if it is implemented. 0: MRL Closed 1: MRL Open If Hotplug is implemented through VPP, the correct polarity of the external MRL sensor in the motherboard should be translated to map to the encodings as defined in this register field.
4	0x0	RW/1C/V	Command Completed (CC) This bit is set when the hot-plug controller completes an issued command and is ready to accept a new command. It is subsequently cleared by software after the field has been read and processed. If Command Completed notification is supported, then the No Command Completed Support bit in the Slot Capabilities register should be 0.
3	0x0	RW/1C/V	Presence Detect Changed (PDC) This bit is set by the root port when the PD bit changes state.
2	0x0	RW/1C/V	MRL Sensor Changed (MSC) This bit is set when an MRL Sensor Changed event is detected. It is subsequently cleared by software after the field has been read and processed. On-board logic per slot must set the VPP signal corresponding to this bit inactive if the FF/system does not support out-of-band presence detect.
1	0x0	RW/1C/V	Power Fault Detected (PFD) This bit is set when a power fault event is detected by the power controller. It is subsequently cleared by software after the field has been read and processed. On-board logic per slot must set the VPP signal corresponding to this bit inactive if the FF/system does not support out-of-band presence detect.
0	0x0	RW/1C/V	Attention Button Pressed (ABP) This bit is set when the Attention Button is pressed. It is subsequently cleared by software after the field has been read and processed. On-board logic per slot must set the VPP signal corresponding to this bit inactive if the FF/system does not support out-of-band presence detect. Design should implement this as an edge detection logic in the chipset/platform to recognize a 0 -> 1 transition as an ABP event. Due to the long time frames for human interaction, software could potentially have serviced and cleared this event while the operator is pressing the Attention Button. For instance, if the user presses the Attention Button that lasts for 2ms and the VPP sampling rate is, say 100us and if the Interrupt Service routine (ISR) processes and clears the ABP in 100us, there could be up to 10 (i.e 2000/(100+100)) different interrupts for the same event. Hardware must only generate 1 interrupt for every ABP event by treating it as edge based rather than level based event.