Virtual Channel 1 Resource Status (V1STS) – Offset 2A6 - 1.3 - ID:767625 | 12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

Introduction
Processor Configuration Register Definitions and Address Ranges
D0:F0 Host Bridge and DRAM Controller - DMIBAR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - DMIBAR Registers (part 2)
- DMI VCm Resource Control (DMIVCMRCTL_0_0_0_DMIBAR)
D0:F0 Host Bridge and DRAM Controller - GFXVTBAR Registers
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 1)
- GFX VT Range Base Address Register (GFXVTBAR_0_0_0_MCHBAR_NCU)
- VT DMI PEG VC0 Range Base Address Register (VTDPVC0BAR_0_0_0_MCHBAR_NCU)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 3)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 5)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - PXPEPBAR PCI Express Egress Port Registers
- Egress Port Virtual Channel Control (EPPVCCTL_0_0_0_PXPEPBAR)
- Egress Port Element Declaration Capability (EPESD_0_0_0_PXPEPBAR)
D0:F0 Host Bridge and DRAM Controller - REGBAR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - REGBAR Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR Registers
D1:F0-1 PCI Express* Controller Registers
D10:F0 Platform Monitoring Technology (PMT) Registers
D13:F0 USB Host Controller (xHCI) Registers
D13:F0 USB Host Controller MBAR Registers
D13:F1 USB Device Controller (xDCI) Configuration Registers
D13:F2-3 Thunderbolt DMA Device Registers
D14:F0 Volume Management Device
D14:F0 Volume Management Device MEMBAR2 Registers
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology Registers
D5:F0 Image Processing Unit Registers
D6:F0 PCI Express* Controller Registers (part 1)
D6:F0 PCI Express* Controller Registers (part 2)
- Feature Control 2 (FCTL2)
D7:F0-3 Thunderbolt PCI Express* Controller Registers
D8:F0 Gauss Newton Algorithm Registers

Virtual Channel 1 Resource Status (V1STS) – Offset 2A6

Virtual Channel 1 Resource Status

Bit Range	Default	Access	Field Name and Description
15:2	0x0	RO	Reserved (RSVD_M) Reserved.
1	0x0	RO/V	VC Negotiation Pending (NP) This bit indicates whether the Virtual Channel negotiation (initialization or disabling) is in pending state. When this bit is Set by hardware, it indicates that the VC resource is still in the process of negotiation. This bit is Cleared by hardware after the VC negotiation is complete. For a non-default Virtual Channel, software may use this bit when enabling or disabling the VC. For the default VC, this bit indicates the status of the process of Flow Control initialization. Before using a Virtual Channel, software must check whether the VC Negotiation Pending bits for that Virtual Channel are Clear in both components on a Link.
0	0x0	RO	Function Arbitration Table Status (FATS) This bit indicates the coherency status of the Function Arbitration Table associated with the VC resource. This bit is valid only when the Function Arbitration Table is used by the selected Function Arbitration for the VC resource. This bit is Set by hardware when any entry of the Function Arbitration Table is written to by software. This bit is Cleared by hardware when hardware finishes loading values stored in the Function Arbitration Table after software sets the Load FunctionArbitration Table bit. Default value of this bit is 0b

Bit Range

Default

Access

Field Name and Description

15:2

0x0

Reserved (RSVD_M)

Reserved.

0x0

RO/V

VC Negotiation Pending (NP)

This bit indicates whether the Virtual Channel negotiation (initialization or disabling) is in pending state.
When this bit is Set by hardware, it indicates that the VC resource is still in the process of negotiation.
This bit is Cleared by hardware after the VC negotiation is complete.
For a non-default Virtual Channel, software may use this bit when enabling or disabling the VC.
For the default VC, this bit indicates the status of the process of Flow Control initialization.
Before using a Virtual Channel, software must check whether the VC Negotiation Pending bits for that Virtual Channel are Clear in both components on a Link.

0x0

Function Arbitration Table Status (FATS)

This bit indicates the coherency status of the Function Arbitration Table associated
with the VC resource.
This bit is valid only when the Function Arbitration Table is used by the selected Function Arbitration for the VC resource.
This bit is Set by hardware when any entry of the Function Arbitration Table is written to by software.
This bit is Cleared by hardware when hardware finishes loading values stored in the Function Arbitration Table after software sets the Load FunctionArbitration Table bit.
Default value of this bit is 0b

DPC Extended Capability Header (DPCECH)

Virtual Channel 1 Resource Control (V1CTL) DPC Extended Capability Header (DPCECH)