XHC Latency Tolerance Parameters LTV Control 2 (XLTP_LTV2) – Offset 8178 - 1.3 - ID:767625 | 12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

12th Generation Intel® Core™ Processors Datasheet Volume 2 of 2

ID	Date	Version	Classification
767625	07/13/2023		Public

XHC Latency Tolerance Parameters LTV Control 2 (XLTP_LTV2) – Offset 8178

XHC Latency Tolerance Parameters LTV Control 2

Bit Range	Default	Access	Field Name and Description
31:18	0x0	RW	Reserved (RSVD) Reserved
17	0x0	RW	Enable Sending Zero LTR message based on run125 (RUN125_IN_LTR_EN) When set, LTR manager will send Zero LTR message upon run125 assertion. And, recomputes and send another LTR upon run125 deassertion
16	0x0	RW	Non Offload Active Periodic TTE Counter Clearing Disable (NONOFLD_ACTV_PRDC_TTE_CNT_CLR_DIS) Setting this bit will disable clearing Non-offload active periodic TTE counter based on TTE Idle indicator
15	0x0	RW	xHC Engine active Propogation Into ux_pmcm_run125 (ENAB_NON_DMA_ENGINE_ACTIVE) This register enables/disables the non DMA related memory traffic to PMC via the xHC active indication. 0: xHC Engine non DMA active is NOT propagated to PMC 1: xHC Engine non DMA active is propagated to PMC
14	0x0	RW	Audio Offload USB2 Resume to DMA Active Mapping Enable (ADO_USB2RES_DMAACTV_MAP_EN) Enables USB2 Port Resume Influence on 'XHCI DMA Active' indication (i.e. Run 125) for Ports Handling Audio Offload. 0 - A USB2 port involved with Audio Offload will NOT influence the XHCI DMA Active indication through USB2 Resume (i.e. USB2 resume for the associated port is not consumed when generating XHCI DMA Active). 1 - A USB2 port involved with Audio Offload will influence (legacy mode) the XHCI DMA Active indication through USB2 Resume (i.e. USB2 resume for the associated port is not consumed when generating XHCI DMA Active). Note: When this field is '0' will allow for a different field to determine what constitutes Audio Offload involvemen The different field is located at 0x8174[13]
13	0x0	RW	Audio Offload USB2 Resume to DMA Active Mask Policy (ADO_USB2RES_DMAACTV_MASK_POLICY) Defines the conditions required for what constitutes Audio Offload involvement for appropriate masking of USB2 Resume on 'XHCI DMA Active' indication (i.e. Run 125) for Ports Handling Audio Offload. 0 - Mask USB2 Resume from asserting the XHCI DMA Active if the particular port going through resume is engaged in Audio Offload while an Audio Offload DB is active (i.e. Audio Offload is connected and active). 1 - Mask USB2 Resume from asserting the XHCI DMA Active if the particular port going through resume is engaged in Audio Offload (i.e. Audio Offload is connected) irrespective of a DB being active/idle.
12:0	0x17FF	RW	LTV Limit (LTV_LMT) This register defines a maximum LTR value that is allowed to be advertised to the PMC. This is meant to be used as a mitigation if issues are discovered with the LTR values generated by the XHC using the defined algorithms. If the LTR value of the XHC is larger than the value in this register field, the value in this field is sent to the PMC instead. Default value is the highest possible - 101b 12:10: Latency Multiplier Field 000b - Value times 1 ns 001b - Value times 32 ns 010b - Value times 1,024 ns 011b - Value times 32,768 ns 100b - Value times 1,048,576 ns 101b - Value times 33,554,432 ns 110b-111b - Not Permitted 9:0: Latency Value Default = 3FFh