13th Generation Intel® Core™ Processors Datasheet, Volume 2 of 2
ID | Date | Version | Classification |
---|---|---|---|
767624 | 07/13/2023 | Public |
Cache Line Size, Master Latency Timer, Header Type and BIST (CACHE_LINE_SIZE) – Offset c
Cache Line Size, Master Latency Timer, Header Type and BIST
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0b | RO | Builtin Self Test (BIST) Hardwired to 0x0. This device does not support BIST. |
30:24 | 0h | RO | Reserved |
23:16 | 0h | RO | Header Type (HEADER_TYPE) This device implements a Type 0 configuration header. |
15:8 | 0h | RO | Master Latency Timer (MASTER_LATENCY_TIMER) This register is also referred to as Primary Latency Timer for Type 1 Configuration Space header Functions. |
7:0 | 0h | RO | Cache Line Size (CACHE_LINE_SIZE) The Cache Line Size register is set by the system firmware or the operating system to system cache line size. |