31

0b

RO

Detected Parity Error (DETECTED_​PARITY_​ERROR)

Not implemented.

30

0b

RO

Signaled System Error (SIGNALED_​SYSTEM_​ERROR)

This bit is set when the device has detected an un-correctable error and reported it via SERR message over sideband.
This requires SERR Enable bit to be set in Command register.
This device does not implement this bit and it is hardwired to a 0.

29

0b

RO

Received Master Abort (RECEIVED_​MASTER_​ABORT_​STATUS)

This bit is set when device receives a Completion transaction with Unsupported Request completion status.
No error will be reported.

28

0b

RO

Received Target Abort (RECEIVED_​TARGET_​ABORT_​STATUS)

This bit is set when device receives a Completion transaction with Completer Abort completion status.
No error will be reported.

27

0b

RO

Signaled Target Abort (SIGNALED_​TARGET_​ABORT_​STATUS)

Set by the device when aborting a request that violates the device programming model.
When SERR Enable is set SERR message will be send over sideband.
Device will not generate a Target Abort DMI completion packet or Special Cycle, and therefore it has no need to implement this bit.

26:25

0h

RO

Reserved

24

0b

RO

Master Data Parity Error (MASTER_​DATA_​PARITY_​ERROR)

This bit is Set by a Requester if the Parity Error Response bit in the Command register is 1b and
either of the following two conditions occurs:

* Requester receives a Completion marked poisoned
* Requester poisons a write Request

If the Parity Error Response bit is 0b, this bit is never Set.

23:21

0h

RO

Reserved

20

1b

RO

Capabilities List (CAPABILITIES_​LIST)

This optional read-only bit indicates whether or not this device implements the pointer for a New Capabilities linked list at offset 34h.
A value of zero indicates that no New Capabilities linked list is available. A value of one indicates that the value read at offset 34h is a pointer in Configuration Space to a linked list of new capabilities.
This device does support capabilities.

19

0b

RO

Interrupt Status (INTERRUPT_​STATUS)

Reflects the state of the interrupt pin at the input of the enable/disable circuit.
When the interrupt is asserted, and cleared when the interrupt is cleared (independent of the state of Interrupt Disable bit in command register.
This bit is only associated with the INTx messages and has no meaning if the device is using MSI.

18:11

0h

RO

Reserved

10

0b

RO

Interrupt Disable (INTERRUPT_​DISABLE)

Disables the function to generate INTx interrupt. A value of 0 enables the function to generate INTA messages.
Note: this bit has no effect on MSI generation.
Since this device does not generate interrupts, this bit is set to 0x0.

9

0h

RO

Reserved

8

0b

RO

SERR Reporting Enable (SERR_​ENABLE)

Setting this bit enables the generation of System Error messages.
Not implemented by this device.

7

0h

RO

Reserved

6

0b

RO

Parity Error Response Enable (PARITY_​ERROR_​RESPONSE)

This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register.
A Root Complex Integrated Endpoint that is not associated with a Root Complex Event Collector is permitted to hardwire this bit to 0b.

5:3

0h

RO

Reserved

2

0b

RO

Bus Master Enable (BUS_​MASTER_​ENABLE)

Controls the ability of a PCI Express Endpoint to issue Memory and I/O Read/Write Requests, and the ability of a Root or Switch Port to forward Memory and I/O Read/Write Requests in the Upstream direction.
Endpoints:

• When this bit is Set, the PCI Express Function is allowed to issue Memory or I/O Requests.
  
• When this bit is Clear, the PCI Express Function is not allowed to issue any Memory or I/O Requests.
  
• Note that as MSI/MSI-X interrupt Messages are in-band memory writes, setting the Bus Master Enable bit to 0b disables MSI/MSI-X interrupt Messages as well.
  Requests other than Memory or I/O Requests are not controlled by this bit.
  Default value of this bit is 0b.
  This bit is hardwired to 0b if a Function does not generate Memory or I/O Requests.

1

0b

RW

Memory Space Enable (MEMORY_​SPACE_​ENABLE)

When set, Memory Space Decoding is enabled and memory transactions targeting the device are accepted
Note: The MSE has to be set to accept any memory transaction on the primary interface targeting any of this device.

0

0h

RO

Reserved