13th Generation Intel® Core™ Processors Datasheet, Volume 2 of 2
ID | Date | Version | Classification |
---|---|---|---|
767624 | 07/13/2023 | Public |
Device Control (DCTL) – Offset 48
Device Control
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15 | 0h | RO | Reserved |
14:12 | 000b | RO | Max Read Request Size (MRRS) Hardwired to 0. |
11 | 0b | RO | Enable No Snoop (ENS) Not supported. The root port will never issue non-snoop requests. |
10 | 0b | RW/P | Aux Power PM Enable (APME) Must be RW for OS testing. The OS will set this bit to '1' if the device connected has detected aux power. It has no effect on the root port otherwise. |
9 | 0b | RO | Phantom Functions Enable (PFE) Not supported |
8 | 0b | RO | Extended Tag Field Enable (ETFE) Not supported |
7:5 | 001b | RW | Max Payload Size (MPS) The root port supports up to 256B max payload. |
4 | 0b | RO | Enable Relaxed Ordering (ERO) Not supported |
3 | 0b | RW | Unsupported Request Reporting Enable (URE) When set, allows signaling ERR_NONFATAL, ERR_FATAL, or ERR_COR to the Root Control register when detecting an unmasked Unsupported Request (UR). An ERR_COR is signaled when a unmasked Advisory Non-Fatal UR is received. An ERR_FATAL, ERR_or NONFATAL, is sent to the Root Control Register when an uncorrectable non-Advisorary UR is received with the severity set by the Uncorrectable Error Severity register. |
2 | 0b | RW | Fatal Error Reporting Enable (FEE) Enables signaling of ERR_FATAL to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting. |
1 | 0b | RW | Non-Fatal Error Reporting Enable (NFE) When set, enables signaling of ERR_NONFATAL to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting. |
0 | 0b | RW | Correctable Error Reporting Enable (CEE) When set, enables signaling of ERR_CORR to the Root Control register due to internally detected errors or error messages received across the link. Other bits also control the full scope of related error reporting. |