31:24

1h

RO/V

Port Number (PN)

Indicates the port number for the root port. This value is different for each implemented port:
Port# Value of PN field
1) 01h
2) 02h
3) 03h
:
:
X) 0Xh
Note: Depending on the platform, the number of Root Ports supported may vary. In this case, the encodings defined in this register will be scaled accordingly.

23

0h

RO

Reserved

22

1b

RW/O

ASPM Optionality Compliance (ASPMOC)

This bit must be set to 1b for PCIe 3.0 compliant port.

Components implemented against certain earlier versions of this specification will have this bit set to 0b.

Software is permitted to use the value of this bit to help

determine whether to enable ASPM or whether to run ASPM compliance tests.

21

1b

RO

Link Bandwidth Notification Capability (LBNC)

This port supports Link Bandwidth Notification status and interrupt mechanisms.

20

1b

RO

Link Active Reporting Capable (LARC)

This port supports the optional capability of reporting the DL_​Active state of the Data Link Control and Management State Machine.

19

0b

RO

Surprise Down Error Reporting Capable (SDERC)

Set to 0 to indicate the Root Port does not support Surprise Down Error Reporting

18

0b

RO

Clock Power Management (CPM)

0' Indicates that root ports do not support the CLKREQ# mechanism.

17:15

010b

RW/O

L1 Exit Latency (EL1)

Indicates an exit latency of 2us to 4us.
0: Less than 1 us
1: 1 us to less than 2 us
2: 2 us to less than 4 us
3: 4 us to less than 8 us
4: 8 us to less than 16 us
5: 16 us to less than 32 us
6: 32 us to 64 us
7: More than 64 us
Note: If power management (e.g PLL shutdown) is enabled, BIOS should program this latency to comprehend PLL lock latency.

14:12

100b

RO/V

L0s Exit Latency (EL0)

Indicates an exit latency based upon common-clock configuration:

LCTL.CCC Value

0 MPC.UCEL

1 MPC.CCEL

11:10

11b

RW/O

Active State Link PM Support (APMS)

Indicates the level of active state power management on this link
Bits Definition
0: No ASPM Support
1: L0s Supported
2: L1 Supported
3: L0s and L1 Supported

9:4

000001b

RO/V

Maximum Link Width (MLW)

Indicates the maximum link width of the link

0x1: x1 Link Width

0x2: x2 Link Width

0x4: x4 Link Width

0x8: x8 Link Width

3:0

0000b

RO/V

Max Link Speed (MLS)

This field indicates the maximum Link speed of the associated Port.
The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the maximum Link speed.
Defined encodings are:
1: Supported Link Speeds Vector field bit 0.
2: Supported Link Speeds Vector field bit 1.
3: Supported Link Speeds Vector field bit 2.
4: Supported Link Speeds Vector field bit 3.
5: Supported Link Speeds Vector field bit 4.
6: Supported Link Speeds Vector field bit 5.
7: Supported Link Speeds Vector field bit 6.
All other encodings are reserved.
This field reports a value of 0001b if GEN1 data rate is supported but both GEN2 and GEN3 data rate support are disabled through PCI Express Speed Limit setting or MPC.PCIESD register.
This field reports a value of 0010b if both GEN1 and GEN2 data rate are supported but GEN3 data rate support is disabled through PCI Express Speed Limit setting or MPC.PCIESD register.
Otherwise, this field reports a value of 0011b.