63

0b

RW/L

Package Limitation #2 Lock (PKG_​PWR_​LIM_​LOCK)

When set, all settings in this register are locked and are treated as Read Only.
This bit will typically set by BIOS during boot time or resume from Sx.

62:48

0h

RO

Reserved

47

0b

RW/L

Package Limitation #2 Enable (PKG_​PWR_​LIM_​2_​EN)

This bit enables/disables Package Limitation #2 (PL2).
0b: Package Power Limit 2 is Disabled
1b: Package Power Limit 2 is Enabled

46:32

0h

RW/L

Package Power Limitation #2 (PKG_​PWR_​LIM_​2)

This field indicates the power limitation #2.
The unit of measurement is defined in MSR PACKAGE_​POWER_​SKU_​UNIT[PWR_​UNIT].

31:24

0h

RO

Reserved

23:17

0000000b

RW/L

Package Limitation #1 Time Window (PKG_​PWR_​LIM_​1_​TIME)

Specifies the time window used to calculate average power for PL1 and PL2.
The timing interval window is Floating Point number given by 1.x * power(2,y).
x = PKG_​PWR_​LIM_​1_​TIME[23:22]
y = PKG_​PWR_​LIM_​1_​TIME[21:17]
The unit of measurement is defined in MSR PACKAGE_​POWER_​SKU_​UNIT[TIME_​UNIT].
The maximal time window is bounded by MSR PACKAGE_​POWER_​SKU[PKG_​MAX_​WIN].
The minimum time window is 1 unit of measurement (as defined above).

16

0b

RW/L

Package Clamping limitation #1 (PKG_​CLMP_​LIM_​1)

Allows going below P1.
0b: Power limit throttling is limited between base frequency (P1) and Max turbo frequency (P0).
1b: Power limit throttling is not limited.

15

0b

RW/L

Package Power Limit 1 Enable (PKG_​PWR_​LIM_​1_​EN)

This bit enables/disables Package Power Limit 1.
0b: Package Power Limit 1 is Disabled
1b: Package Power Limit 1 is Enabled

14:0

0h

RW/L

Package Power Limit 1 (PKG_​PWR_​LIM_​1)

This field indicates the power limitation #1.
The unit of measurement is defined in PACKAGE_​POWER_​SKU_​UNIT_​MSR[PWR_​UNIT].