15

0b

RO

Detected Parity Error (DPE)

The DTT device does not implement this bit and it is hardwired to a 0.

14

0b

RO

Signaled System Error (SSE)

This bit is hardwired to zero.
The DTT Device never asserts SERR#, and therefore it has no need to implement this bit.

13

0b

RO

Received Master Abort Status (RURS)

The DTT device does not implement this bit and it is hardwired to a 0.

12

0b

RO

Received Target Abort Status (RCAS)

The DTT device does not implement this bit and it is hardwired to a 0.

11

0b

RO

Signaled Target Abort Status (STAS)

This bit is hardwired to 0.
The DTT Device will not generate a Target Abort DMI completion packet or Special Cycle, and therefore it has no need to implement this bit.

10:9

00b

RO

DEVSEL# Timing Status (DEVT)

These bits are hardwired to 0.
Device 4 does not physically connect to PCI_​A.

8

0b

RO

Master Data Parity Error Detected (DPD)

This bit is hardwired to 0.
PERR signaling and messaging are not implemented by the DTT Device, and therefore it has no need to implement this bit.

7

1b

RO

Fast Back to Back Capable (FB2B)

This bit is hardwired to 1.
Device 4 does not physically connect to PCI_​A, so this bit is set to 1 (indicating fast back-to-back capability) so that the optimum setting for PCI_​A is not limited by the DTT Device.

6

0h

RO

Reserved

5

0b

RO

Primary 66 MHz Capable (PCI66M)

The DTT device does not implement this bit and it is hardwired to a 0.

4

1b

RO

Capabilities List (CLIST)

This bit is set to 1 to indicate that the register at 34h provides an offset into the function. PCI
Configuration Space containing a pointer to the location of the first item in the list.

3

0b

RW/V/L

Interrupt Status (IS)

Reflects the state of the INTA# signal at the input of the enable/disable circuit. This bit is set
by HW to 1 when the INTA# is asserted and reset by HW to 0 after the interrupt is cleared (independent of the
state of the Interrupt Disable bit in the 0.4.0.PCICMD register).

2:0

0h

RO

Reserved