63

0h

RO

Reserved

62:59

0010b

RW

Derating Extensions (derating_​ext)

Holds LPDDR timing parameters derating tRAS, tRRD, tRP and tRCD in tCK (WCK for LPDDR5) cycles.
When LPDDR is hot, this value is added to the appropriate timing parameters.
For non LP devices program the field to 0.
Supported range is 0-4.

58:51

8h

RW

tRCD Timing Parameter (tRCD)

Holds DDR timing parameter tRCD
ACT to CAS (RD) same bank minimum delay in tCK (WCK for LPDDR5) cycles.
Supported range is 8-59.

50:42

1ch

RW

tRAS Timing Parameter (tRAS)

Holds DDR timing parameter tRAS.
ACT to PRE same bank minimum delay in tCK (WCK for LPDDR5) cycles.
For DDR/LPDDR Supported range is 28-160

41:32

18h

RW

tWRPRE Timing Parameter (tWRPRE)

Holds DDR timing parameter tWRPRE.
WR to PRE same bank minimum delay in tCK (WCK for LPDDR5) cycles.
Supported range is 18-240.

31:24

8h

RW

tRCDW reg (tRCDW)

Holds DDR timing parameter tRCDW, tRCD for writes at LPDDR5x
ACT to CAS (WR) same bank minimum delay in tCK (WCK for LPDDR5) cycles.
Supported range is 8-59.

23:20

0100b

RW

tPPD Timing Parameter (tPPD)

Holds DDR timing parameter tPPD.
PRE/PREALL to PRE/PREALL (same rank) minimum delay in tCK (WCK for LPDDR5) cycles.
Supported range is 4-7.
Note this register is not used in DDR5;

19:13

0000110b

RW

tRDPRE Timing Parameter (tRDPRE)

Holds DDR timing parameter tRDPRE.
RD to PRE same bank minimum delay in tCK (WCK for LPDDR5) cycles.
Supported range is 4-44.

12:8

00000b

RW

tRPab_​ext Timing Parameter (tRPab_​ext)

Holds the value of tRPab-tRPpb for LPDDR in tCK (WCK for LPDDR5) cycles.
LPDDR technologies requires a longer time from PREALL to ACT vs. PRE to ACT, the offset between the two should be programmed to this field.
When using DDR4 this field should be programmed to 0.
For LPDDR4 the following restrictions apply: For single/dual rank sub channels tRP-tRPab_​ext > 6. For three/four ranks sub channels tRP-tRPab_​ext > 8.
Supported range is 0-12.

7:0

8h

RW

tRP Timing Parameter (tRP)

Holds DDR timing parameter tRP (and tRCD).
PRE to ACT same bank minimum delay in tCK (WCK for LPDDR5) cycles.
ACT to CAS (RD or WR) same bank minimum delay in tCK (WCK for LPDDR5) cycles.
Supported range is 8-60.