RD to RD Timings (TC_RDRD_0_0_0_MCHBAR) – Offset e00c - 1.3 - ID:767624 | 13th Generation Intel® Core™ Processors Datasheet, Volume 2 of 2

Introduction
Processor Configuration Register Definitions and Address Ranges
D0:F0 Host Bridge and DRAM Controller - DMIBAR Registers
D0:F0 Host Bridge and DRAM Controller - GFXVTBAR Registers
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - GTTMMADR Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 1)
- Revision ID (RID_0_0_0_PCI)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 1)
- GFX VT Range Base Address Register (GFXVTBAR_0_0_0_MCHBAR_NCU)
- VT DMI PEG VC0 Range Base Address Register (VTDPVC0BAR_0_0_0_MCHBAR_NCU)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 3)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller Registers (part 5)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management Registers (part 2)
D0:F0 Host Bridge and DRAM Controller - PXPEPBAR PCI Express Egress Port Registers
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR Registers
D1:F0-1 PCI Express* Controller Registers
D10:F0 Platform Monitoring Technology (PMT) Registers
D14:F0 Volume Management Device
D14:F0 Volume Management Device MEMBAR2 Registers
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology Registers
D6:F0 PCI Express* Controller Registers
D8:F0 Gauss Newton Algorithm Registers

RD to RD Timings (TC_RDRD_0_0_0_MCHBAR) – Offset e00c

DDR timing constraints related to timing between read and read transactions

Bit Range	Default	Access	Field Name and Description
31:24	4h	RW	tRDRD Different DIMM (tRDRD_dd) Minimum delay from RD to RD to the other DIMM in tCK (WCK for LPDDR5) cycles. Supported range is 4-54.
23:16	4h	RW	tRDRD Different Rank (tRDRD_dr) Minimum delay from RD to RD to the other rank in the same DIMM in tCK (WCK for LPDDR5) cycles. Supported range is 4-54.
15	0h	RO	Reserved
14:8	0000100b	RW	tRDRD Different Group (tRDRD_dg) LPDDR4/LPDDR5: Minimum delay from RD to RD to different banks in tCK (WCK for LPDDR5) cycles. DDR4/DDR5: Minimum delay from RD to RD to different bank groups in tCK cycles. Supported range is 4-54.
7	1b	RW	Allow 2 Cycle B2B LPDDR (Allow_2cyc_B2B_LPDDR) LPDDR4/LPDDR5: in MPR mode reads work on BL16. In Gear4 this means 2 DCLKs apart reads. Clearing this bit will prevent LPDDR from schedule a read 2 DCLKs after another read.
6:0	0000100b	RW	tRDRD Same Group (tRDRD_sg) LPDDR4/LPDDR5: Minimum delay from RD to RD to the same bank in tCK (WCK for LPDDR5) cycles. DDR4/DDR5: Minimum delay from RD to RD to the same bank group in tCK cycles. Supported range is 4-54.

RD to WR Timings (TC_RDWR_0_0_0_MCHBAR)

ACT Command Timing (TC_ACT_0_0_0_MCHBAR) RD to WR Timings (TC_RDWR_0_0_0_MCHBAR)