13th Generation Intel® Core™ Processors Datasheet, Volume 2 of 2
ID | Date | Version | Classification |
---|---|---|---|
767624 | 07/13/2023 | Public |
Type-C Sub-system Device Enable (TCSS_DEVEN_0_0_0_MCHBAR_IMPH) – Offset 7090
Allows for enabling/disabling of Type-C PCI devices and functions that are within the CPU package. The table below the bit definitions describes the behavior of all combinations of transactions to devices controlled by this register. All the bits in this register are Intel TXT Lockable.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:14 | 0h | RO | Reserved |
13 | 1b | RW/L | Thunderbolt DMA3 Enable (TBT_DMA3_EN) 0: DMA3 is disabled and hidden. |
12 | 1b | RW/L | Thunderbolt DMA2 Enable (TBT_DMA2_EN) 0: DMA2 is disabled and hidden. |
11 | 1b | RW/L | Thunderbolt DMA1 Enable (TBT_DMA1_EN) 0: DMA1 is disabled and hidden. |
10 | 1b | RW/L | Thunderbolt DMA0 Enable (TBT_DMA0_EN) 0: DMA0 is disabled and hidden. |
9 | 1b | RW/L | xDCI Enable (xDCI_EN) 0: xDCI is disabled and hidden. |
8 | 1b | RW/L | xHCI Enable (xHCI_EN) 0: xHCI is disabled and hidden. |
7 | 1b | RW/L | PCIe7 Enable (PCIE7_EN) 0: TypeC PCIE Root Port 7 is disabled |
6 | 1b | RW/L | PCIe6 Enable (PCIE6_EN) 0: TypeC PCIE Root Port 6 is disabled |
5 | 1b | RW/L | PCIe5 Enable (PCIE5_EN) 0: TypeC PCIE Root Port 5 is disabled |
4 | 1b | RW/L | PCIe4 Enable (PCIE4_EN) 0: TypeC PCIE Root Port 4 is disabled |
3 | 1b | RW/L | PCIe3 Enable (PCIE3_EN) 0: TypeC PCIE Root Port 3 is disabled |
2 | 1b | RW/L | PCIe2 Enable (PCIE2_EN) 0: TypeC PCIE Root Port 2 is disabled |
1 | 1b | RW/L | PCIe1 Enable (PCIE1_EN) 0: TypeC PCIE Root Port 1 is disabled |
0 | 1b | RW/L | PCIE0 Enable (PCIE0_EN) 0: TypeC PCIE Root Port 0 is disabled |