Intel® Core™ Ultra Processors for H-series and U-series Platforms CFG and MEM Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 795258 | 12/14/2023 | Public |
A newer version of this document is available. Customers should click here to go to the newest version.
Power Management Control and Status (PMCS) – Offset d4
Power Management Control and Status
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:16 | 0h | RO | Reserved |
| 15 | 0h | RW/1C/V | Power Management Event Status (PMES) Not used. |
| 14:13 | 0h | RO | Data Scale (DS) Not used |
| 12:9 | 0h | RO | Data Scale (DSEL) Not used |
| 8 | 0h | RO | Power Management Event Enable (PMEEN) Power Management Event Enable |
| 7:4 | 0h | RO | Reserved |
| 3 | 1h | RO | No Soft Reset (NSR) This read-only bit indicates that the device does not lose internal state on a D3hot to D0 transition. This means:
|
| 2 | 0h | RO | Reserved |
| 1:0 | 0h | RW/V | Power State (PS) Power management is implemented by writing to control registers in the PUNIT. This field may be programmed by the software driver, but no action is taken based on writing to this field. |