Intel® Core™ Ultra Processors for H-series and U-series Platforms CFG and MEM Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 795258 | 12/14/2023 | Public |
A newer version of this document is available. Customers should click here to go to the newest version.
Protected Audio Video Path Control (PAVPC_0_0_0_PCI) – Offset 58
All the bits in this register are locked by Intel TXT. When locked the R/W bits are RO.
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:20 | 0h | RW/L | (PCMBASE) Sizes supported: 1M, 2M, 4M and 8M. |
| 19:7 | 0h | RO | Reserved |
| 6 | 0h | RW/L | ASMF method enabled (ASMFEN) 0: Disabled (default) |
| 5 | 0h | RO | Reserved |
| 4 | 0h | RW/L | Override of Unsolicited Connection State Attack and Terminate. (OVTATTACK) 0: Disable Override. Attack Terminate allowed. |
| 3 | 0h | RW/L | (HVYMODSEL) This bit is applicable only for PAVP2 operation modePAVP3 mode, this one type boot time programming has been replaced by per-App |
| 2 | 0h | RW/L | (PAVPLCK) This bit locks all writable contents in this register when set (including itself). |
| 1 | 0h | RW/L | (PAVPE) 0: PAVP functionality is disabled. |
| 0 | 1h | RW/L | (PCME) This field enables Protected Content Memory within Graphics Stolen Memory. |