63

1h

RO

Enhanced Set Root Table Pointer Support (ESRTPS)

0: Hardware does not invalidate all DMA remapping hardware translation caches as part of SRTP flow.
1: Hardware invalidates all DMA remapping hardware translation caches as part of SRTP flow.

62

1h

RO

Enhanced Set Interrupt Root Table Pointer Support (ESIRTPS)

0: Hardware does not invalidate all Interrupt remapping hardware translation caches as part of SIRTP flow.
1: Hardware invalidates all Interrupt remapping hardware translation caches as part of SIRTP flow.

61

0h

RO

Enhanced Command Support (ECMDS)

Refer to VT-d specification

60

0h

RO/V

First Level 5-level Paging (FL5LP)

0: Hardware does not support 5-level paging for requests-with-PASID subject to first-level translation.
1: Hardware supports 5-level paging for requests-with-PASID subject to first-level translation.

59

1h

RO/V

Posted Interrupt Support (PI)

0: Hardware does not support Posting of Interrupts.
1: Hardware supports Posting of Interrupts.
Hardware implementations reporting this field as Set must also report Interrupt Remapping support (IR field in Extended Capability Register)

58:57

0h

RO

Reserved

56

1h

RO/V

First Level 1-GByte Page Support (FL1GP)

A value of 1 in this field indicates 1-GByte page size is supported for first-level translation.

55

1h

RO/V

Read Draining (DRD)

0: Hardware does not support draining of DMA read requests.
1: Hardware supports draining of DMA read requests.

54

1h

RO/V

Write Draining (DWD)

0: Hardware does not support draining of DMA write requests.
1: Hardware supports draining of DMA write requests.

53:48

1eh

RO/V

Maximum Address Mask Value (MAMV)

The value in this field indicates the maximum supported value for the Address Mask (AM) field in the Invalidation Address register (IVA_​REG) and IOTLB Invalidation Descriptor (iotlb_​inv_​dsc) used for invalidations of second-level translation.
This field is valid only when the PSI field in Capability register is reported as Set.

47:40

0h

RO/V

Number of Fault-Recording Registers (NFR)

Number of fault recording registers is computed as N+1, where N is the value reported in this field.
Implementations must support at least one fault recording register (NFR = 0) for each remapping hardware unit in the platform.
The maximum number of fault recording registers per remapping hardware unit is 256.

39

1h

RO/V

Page Selective Invalidation (PSI)

0: Hardware supports only domain and global invalidates for IOTLB.
1: Hardware supports page selective, domain and global invalidates for IOTLB.
Hardware implementations reporting this field as set are recommended to support a Maximum Address Mask Value (MAMV) value of at least 9 (or 18 if supporting 1GB pages with second level translation).

38

0h

RO

Reserved

37:34

3h

RO/V

Second Level Large Page Support (SLLPS)

This field indicates the super page sizes supported by hardware.
A value of 1 in any of these bits indicates the corresponding super-page size is supported. The super-page sizes corresponding to various bit positions within this field are:
0: 21-bit offset to page frame (2MB)
1: 30-bit offset to page frame (1GB)
2: 39-bit offset to page frame (512GB)
3: 48-bit offset to page frame (1TB)
Hardware implementations supporting a specific super-page size must support all smaller super-page sizes, i.e. only valid values for this field are 0000b, 0001b, 0011b, 0111b, 1111b.

33:24

eeh

RO/V

Fault-Recording Register Offset (FRO)

This field specifies the location to the first fault recording register relative to the register base address of this remapping hardware unit.
If the register base address is X, and the value reported in this field is Y, the address for the first fault recording register is calculated as X+(16*Y).

23

0h

RO

Reserved

22

1h

RO/V

Zero Length Read (ZLR)

0: Indicates the remapping hardware unit blocks (and treats as fault) zero length DMA read requests to write-only pages.
1: Indicates the remapping hardware unit supports zero length DMA read requests to write-only pages.
DMA remapping hardware implementations are recommended to report ZLR field as Set.

21:16

29h

RO/V

Maximum Guest Address Width (MGAW)

This field indicates the maximum DMA virtual addressability supported by remapping hardware. The Maximum Guest Address Width (MGAW) is computed as (N+1), where N is the value reported in this field. For example, a hardware implementation supporting 48-bit MGAW reports a value of 47 (101111b) in this field.
If the value in this field is X, untranslated and translated DMA requests to addresses above 2(x+1)-1 are always blocked by hardware. Translations requests to address above 2(x+1)-1 from allowed devices return a null Translation Completion Data Entry with R=W=0.
Guest addressability for a given DMA request is limited to the minimum of the value reported through this field and the adjusted guest address width of the corresponding page-table structure. (Adjusted guest address widths supported by hardware are reported through the SAGAW field).
Implementations are recommended to support MGAW at least equal to the physical addressability (host address width) of the platform.

15:13

0h

RO

Reserved

12:8

4h

RO/V

Supported Adjusted Guest Address Widths (SAGAW)

This 5-bit field indicates the supported adjusted guest address widths (which in turn represents the levels of page-table walks for the 4KB base page size) supported by the hardware implementation.
A value of 1 in any of these bits indicates the corresponding adjusted guest address width is supported. The adjusted guest address widths corresponding to various bit positions within this field are:
0: 30-bit AGAW (2-level page table)
1: 39-bit AGAW (3-level page table)
2: 48-bit AGAW (4-level page table)
3: 57-bit AGAW (5-level page table)
4: Reserved
Software must ensure that the adjusted guest address width used to setup the page tables is one of the supported guest address widths reported in this field.

7

0h

RO/V

Caching Mode (CM)

0: Not-present and erroneous entries are not cached in any of the remapping caches. Invalidations are not required for modifications to individual not present or invalid entries. However, any modifications that result in decreasing the effective permissions or partial permission increases require invalidations for them to be effective.
1: Not-present and erroneous mappings may be cached in the remapping caches. Any software updates to the remapping structures (including updates to not-present or erroneous entries) require explicit invalidation.
Hardware implementations of this architecture must support a value of 0 in this field.

6

1h

RO/V

Protected High-Memory Region (PHMR)

0: Indicates protected high-memory region is not supported.
1: Indicates protected high-memory region is supported.

5

1h

RO/V

Protected Low-Memory Region (PLMR)

0: Indicates protected low-memory region is not supported.
1: Indicates protected low-memory region is supported.

4

0h

RO/V

Required Write-Buffer Flushing (RWBF)

0: Indicates no write-buffer flushing is needed to ensure changes to memory-resident structures are visible to hardware.
1: Indicates software must explicitly flush the write buffers to ensure updates made to memory-resident remapping structures are visible to hardware.

3

0h

RO/V

Advanced Fault Logging (AFL)

0: Indicates advanced fault logging is not supported. Only primary fault logging is supported.
1: Indicates advanced fault logging is supported.

2:0

2h

RO/V

Number of Domains Supported (ND)

0: Hardware supports 4-bit domain-ids with support for up to 16 domains.
1: Hardware supports 6-bit domain-ids with support for up to 64 domains.
2: Hardware supports 8-bit domain-ids with support for up to 256 domains.
3: Hardware supports 10-bit domain-ids with support for up to 1024 domains.
4: Hardware supports 12-bit domain-ids with support for up to 4K domains.
5: Hardware supports 14-bit domain-ids with support for up to 16K domains.
6: Hardware supports 16-bit domain-ids with support for up to 64K domains.
7: Reserved.