Intel® Core™ Ultra Processors for H-series and U-series Platforms CFG and MEM Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 795258 | 07/29/2024 | Public |
SRIOV Control Register (SRIOV_CTRL_0_2_0_PCI) – Offset 328
SR-IOV Control Register.
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 15:6 | 0h | RO | Reserved |
| 5 | 0h | RW/V | VF 10-BIT TAG REQUESTER ENABLE (VF_10B_TAG_REQ_EN) If Set, all VFs must use 10-Bit Tags for all Non-Posted Requests they generate. If Clear, VFs must not use 10-Bit Tags for Non-Posted Requests they generate |
| 4 | 0h | RW | ARI CAPABLE HIERARCHY (ARI_CAPHIER) This bit must be RW in the lowest-numbered PF of the Device and hardwired to 0b in all other PFs. If the value of this bit is 1b, the Device is permitted to locate VFs in Function Numbers 8 to 255 of the captured Bus Number. Otherwise, the Device must locate VFs as if it were a non-ARI Device. This bit is not affected by FLR of any PF or VF. Default value is 0b |
| 3 | 0h | RW/V | VF MEMORY SPACE ENABLE (VF_MSE) SW shall set this bit before setting VF Enable. (to allow VF memory space response) |
| 2 | 0h | RO | VF MIGRATION INTERRUPT ENABLE (VF_MIG_INTR_EN) VF migration is not supported. |
| 1 | 0h | RO | VF MIGRATION ENABLE (VF_MIG_EN) VF migration is not supported. |
| 0 | 0h | RW/V | VF ENABLE (VF_EN) System SW shall set this bit to enable VFs.Note: This bit becomes RO defaulting to 0 if SRIOV is disabled by fuse.Its R/W only when SRIOV is enabled by fuse. System SW shall set this bit to enable VFs. Setting/Clearing this bit shall result in an interrupt to GUC. This allows the GuC and subsequently the PF to take appropriate action to comprehend virtualization. |