ADR Control and Status (ADR_CTRL_STS) – Offset 1960 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
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I3C / I2C / UART / GSPI PCR
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Integrated Sensor Hub (ISH) PCI Configuration
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Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
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RTC Index
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SATA ABAR
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- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
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- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
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SATA Port 0 ABAR
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SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

ADR Control and Status (ADR_CTRL_STS) – Offset 1960

This register contains bits that determine the behavior of the ADR feature. This register is in the RTC power well and is reset by RTCRST#.

Bit Range	Default	Access	Field Name and Description
31:3	0h	RO	Reserved
2	0h	RW/1C/V	ADR Phase 2 Timer Expiration Status (ADR_P2_TIMER_EXP_STS) Hardware reports the time expiration for Phase 2 0: Phase 2 Timer has not expired 1: Phase 2 Timer has expired Write 1 to clear.
1	0h	RW/1C/V	ADR Phase 1 Timer Expiration Status (ADR_P1_TIMER_EXP_STS) Hardware reports the time expiration for Phase 1 0: Phase 1 Timer has not expired 1: Phase 1 Timer has expired Write 1 to clear.
0	0h	RW/1C/V	ADR Reset Status (ADR_RST_STS) When set to '1', this bit indicates that the Automatic DIMM Self-Refresh (ADR) flow was executed during a prior global reset entry. Write 1 to clear.

ACPI Control (ACTL)

Latency Limit Control (LATENCY_LIMIT_CONTROL) ACPI Control (ACTL)

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ADR Control and Status (ADR_CTRL_STS) – Offset 1960