ADR Enable (ADR_EN) – Offset 18f0 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

ADR Enable (ADR_EN) – Offset 18f0

Bit Range	Default	Access	Field Name and Description
31:30	0h	RW/L	ADR GPIO Selection (ADR_GPIO_SEL) This field selects which PM_SYNC GPIO state will be a source of ADR. This input may also be a source of Global Reset based on ADR_GPIO_RST_EN. Encodings: - 00: Reserved - 01: GPIO_B - 10: GPIO_C - 11: Reserved Note: This field is not when two-phase ADR is enabled (ADR_GEN_CFG.ADR_P2_EN == 1) and the ADR trigger is converted to two messages mapped statically to two PM_SYNC GPIO pins. Programming Restriction: The PCH only supports use of CPU_GP_0 as the board-level trigger for ADR. Therefore, this field must be programmed to the PM_SYNC GPIO state which is assigned to CPU_GP_0 in the PM_SYNC_MISC_CFG register (which will be GPIO_B or GPIO_C).
29	0h	RO	Reserved
28	1h	RW/L	Host Partition Reset ADR Enable (HPR_ADR_EN) If this bit is set to '1', PMC FW will set the ADR_RST_STS bit upon receipt of the Reset_Warn_Ack DMI message (when certains conditions are met).
27	0h	RW/L	ADR GPIO Output Enable (ADR_GPIO_OUT_EN) If this bit is 0, the PMC will never drive the ADR GPIO pin as an output. If this bit is 1, the PMC will drive the ADR GPIO pin to 0 when it starts the ADR flow. Note that the ADR pin is bi-direction while this bit is 1. So the PMC will both monitor the pin value, which will trigger the ADR flow if asserted, and will assert the pin if an internal ADR trigger is detected
26	0h	RW/L	ADR Pltaform Acknowledge Enable (ADR_PLT_ACK_EN) This bit enables the PCH to wait for a platform ack signal after ADR_complete is asserted before proceeding to the next step.
25:1	0h	RO	Reserved
0	0h	RW/V/L	ADR Feature Enable (ADR_FEAT_EN) If this bit is a '1' and ADR is supported in the PCH, Automatic DIMM Self-Refresh is enabled. The other bits in this register determine which individual reset sources will be included. Note: This bit must not be set to '1' until PM_SYNC has been fully configured to convey the global reset warning to the processor.