ADR General Configuration (ADR_GEN_CFG) – Offset 1908 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

ADR General Configuration (ADR_GEN_CFG) – Offset 1908

Bit Range	Default	Access	Field Name and Description
31	0h	RW/L	ADR Configuration Lock (ADR_CFG_LOCK) Lock key bit for all the RW/L bits in ADR_GEN_CFG register. Once this bit is set to a 1b, this key bit can not be unlocked without reset. Writing a 0b has no effect on this bit.
30:29	0h	RO	Reserved
28:26	0h	RW/L	ADR Timer Scale (ADR_P2_TIMER_SCALE) This field specifies the tick frequency upon which the timer will increment. Encodings: - 000b: 1 us - 001b: 10 us - 010b: 100 us - 011b: 1 ms - 100b: 10 ms - 101b: 100 ms - 110b: 1 s - 111b: 10 s
25	0h	RW/L	PCH Upstream Fabric Stall (PCH_UPSTRM_FAB_STALL) If this is set, and an ADR flow starts, an indication is flagged to PSF to stall PCH transactions (other than completions) going upstream to CPU. Note, downstream transaction completions will be unaffected. 0: PCH new upstream transactions are not blocked. 1: PCH new upstream transactions (does not include completions) are blocked.
24	0h	RW/L	ADR Complete Source Select (ADR_COMPLETE_SRCSEL) ADR_RST_STS is always source of ADR_COMPLETE. This bit determines the other input into the OR gate. The other input is either: 0: Message from CPU indicating that ADR preparation is done OR ADR timer expiration (whichever happens earlier). 1: ADR timer expiration.
23:20	0h	RW/L	ADR Complete Minimum Assertion Width (ADR_COMPLETE_DELAY_TIMER) This field determines the minimum amount of time, in 2us increments, that the ADR_COMPLETE pin is asserted. Timer will be within +/- 1us of set limit. Values starts from 0us and continue till 30us
19	0h	RW/L	ADR Phase 2 Enable (ADR_P2_EN) This field determines if the phase 2 is enabled. Value 1b0 indicates that the ADR flow has a single phase.
18:11	0h	RW/L	ADR Timer Base (ADR_P2_TIMER_TOV) This field determines the Timeout value used for the ADR timer. The timescale is determined by ADR_P2_TIME_SCALE field. A value of zero bypasses (disables) the timer.
10:8	0h	RW/L	ADR Timer Scale (Tick Frequency) (ADR_P1_TIMER_SCALE) This field specifies the tick frequency upon which the timer will increment. Encodings: - 000b: 1 us - 001b: 10 us - 010b: 100 us - 011b: 1 ms - 100b: 10 ms - 101b: 100 ms - 110b: 1 s - 111b: 10 s\t
7:0	0h	RW/L	ADR Timer Base (ADR_P1_TIMER_TOV) This field determines the Timeout value used for the ADR timer. The timescale is determined by ADR_TIME_SCALE field. A value of zero bypasses (disables) the timer.