AUX Power Management Control (AUX_CTRL_REG1) – Offset 80e0 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

AUX Power Management Control (AUX_CTRL_REG1) – Offset 80e0

AUX Power Management Control

Bit Range	Default	Access	Field Name and Description
31	1h	RW	D3 Hot function enable register (D3_HOT_FXN_EN) This bit is from pin input which is set 1. But we allow software to alter it if it is needed. 1: D3 hot enabled 0: D3 hot not abled.
30	0h	RW	Allow L1 Core Clock Gating (ALL_L1_CORE_CG) When set to 1 allows core clock being gated during L1 state.
29	0h	RW	Allow Engine PHY Status Extension (AL_EP_SEXT) When set to 1 allows the engine to extend PHY status of PCIe PIPE for one more cycle. This is due to the fact that our rate change function has a potential of not being able to sample the phystatus signal.
28	0h	RW	Allow Engine PCIe Rate Change Passing (ALL_EP_RCP) When set to 1 allows the engine to pass PCIe rate change signal as it is from PCIe core to PCIe PHY.
27	0h	RW	Allow Engine PERST Fundamental Reset (AL_PERST_FRST) When set to 1 allow engine to treat PERST# as a foundamental reset
26	0h	RW	Overwrite PCIe P2 to P1 (OVR_PCIE_P2_P1) When set to 1 will overwrite a PCIe powerdown state of P2 to P1.
25	0h	RW	Set Internal SSV 1 (SET_ISSV_1) When set to 1 set the internal SSV to 1.
24	0h	RW	Clear Internal SSV 0 (CLR_ISSV_0) When set to 1 clear the internal SSV to 0.
23	1h	RW	Enable save_restore_enable SW Loading (EN_SRE_SW_LD) This is a bit that enables the save_restore_enable signal being loaded when a software command has set Save bit. This is a debug function.
22	0h	RW	RESERVED (RSVD_1) RESERVED
21	0h	RW	Force save_restore 1 (FORCE_SR1) When set to 1, it will force the save_restore flag to 1. This flag is an bit to ensure that we have masked the update during low power state. If software write this bit to 1, it must write it to 0 in order to resume the normal save and restore function.
20	0h	RW	CFG DISABLE_WARM_RST_DET_specUpPorts (CFG_DIS_WRSTDET_SPECU) 0: Speculative upstream for Debug and SS/SSP port will detect WPR 1: No speculative upstream till port configuration is completed
19	0h	RW	cfg iob drivestrength[1] (CIDS1) Controls the drive strength of the IO buffer
18	0h	RW	cfg iob drivestrength[0] (CIDS0) Controls the drive strength of the IO buffer
17	0h	RW	cfg_dis_arc_RXDP3 (CFG_DIS_ARC_RXDP3) When set to '1' DIsables arc to RXDET_p3 on disc from U2P3/U3
16	0h	RW	cfg clk gate dis (CCGD) 1: Disable USB3 port clock gating 0: Enable USB3 port clock gating
15	1h	RW	Enable CFG RXDET P3 (EN_CFG_RDP3) When set to '1' enable cfg rxdet p3
14	0h	RW	Enable CFG PIPE Reset (EN_CFG_PIPE_RST) When set to '1' enable cfg pipe rst
13	1h	RW	Enable Filter TX Idle (EN_FILT_TX_IDLE) When set to 1 enables a filter function to TX electrical idle signal at PCie PIPE. We have a filter that will set TXelecidle signal of PCIe PIPE to 1 whenever we are in isolation state or power down transition states.
12	1h	RW	Enable Host Engine Generate PME (EN_HE_GEN_PME) This is a global switch to whether or not eable this host engine to generate PME message.
11	1h	RW	Enable Isolation (EN_ISOL) When set to '1' enable isolation
10	1h	RW	Enable L1 Caused P2 Overwrite (EN_L1_P2_OVR) Set 1 to enable a new feature. This new feature is designed to use L1 as a state to identify whether we should do P2 Overwrite or not. We used to use P1 state to identify whether or not to invoke P2 overwrite function.
9	0h	RW	Enable Core Clock Gating (EN_CORE_CG) When set to '1' disable core clock gating based on low power state entered
8	0h	RW	Enable PHY Status Timeout (EN_PHY_STS_TO) When set to '1' enable PHY status timeout function which is designed to cover the PCIePHY issue that we may have not able to detect the PHY status toggle.
7	1h	RW	Ignore aux_pm_en PCIe Core (IGN_APE_PC) When set to '1' ignore the aux_pm_en reg from PCIe core to continue the remote wake/clock switching support
6	1h	RW	Enable P2 Overwrite P1 (EN_P2_OVR_P1) When set to '1' enable P2 overwrite P1 when PCIe core has indicated the transition from P0 to P1. This is to enable entering the even lower power state.
5	1h	RW	Enable P2 Remote Wake (EN_P2_REM_WAKE) When set 1 '1' enable the remote wake function by allowing P2 clock/switching and P2 entering
4:1	0h	RW	Forced PM State (FORCED_PM_STATE) Forced PM state
0	0h	RW	Initiate Force PM State (INIT_FPMS) When set to '1' force PM state to go to the state indicated in bit 4:1

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

AUX Power Management Control (AUX_CTRL_REG1) – Offset 80e0