BIOS Control (BIOS_SPI_BC) – Offset dc - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

BIOS Control (BIOS_SPI_BC) – Offset dc

This register collects bits that were previously distributed in various IPs and input to the SPI controller via discrete wires.

Bit Range	Default	Access	Field Name and Description
31:29	0h	RO	Reserved (RSVD) Reserved.
28	0h	RW/L	Extended BIOS Range Lock (EXT_BIOS_LOCK) When set, prevents BIOS_SPI_BAR1.MEMBAR, EXT_BIOS_EN and EXT_BIOS_LIMIT_OFFSET from being changed. This bit can only be written from 0 to 1 once. This field is only used when the extended BIOS direct read range decoding is supported. (SPI_EXT_BIOS_BAR1_EN=1).
27	0h	RW/L	Extended BIOS Range Enable (EXT_BIOS_EN) When set, enables the extended BIOS range decoding on SPI BAR1.This field is only used when the extended BIOS direct read range decoding is supported. (SPI_EXT_BIOS_BAR1_EN=1). This field is locked when EXT_BIOS_LOCK =1.
26:12	0h	RW/L	Extended BIOS Range Limit Offset (EXT_BIOS_LIMIT_OFFSET) This field defines the offset of the extended BIOS range upper limit from the upper limit of the BIOS region in the flash. This field is only used when the extended BIOS direct read range decoding is supported. (SPI_EXT_BIOS_BAR1_EN=1). This field is locked when EXT_BIOS_LOCK =1.
11	0h	RW/L	Async SMI Enable for BIOS Write Protection (ASE_BWP) When set to '1', the flash controller will generate an SMI when it blocks a BIOS write or erase. The value in this field can be written by software as long as the BIOS Interface Lock-Down (BILD) is not set.
10	0h	RO/V	Asynchronous SMI Status (SPI_ASYNC_SS) Status indication that the SPI Flash Controller has asserted an asynchronous SMI. Hardware clears the bit when it sends the De-assert SMI message. 0: default state 1: SPI flash controller asserted Asynchronous SMI
9	0h	RW/L	OS Function Hide (OSFH) This bit controls read access over IOSF Primary to SPI's Device ID, Vendor ID PCI Config register. This bit does not affect access to any other PCI Config registers. This bit is locked with BILD. Trusted BIOS must set this bit prior to starting the OS. 0 : DeviceID, VendorID can be read 1 : reads to Device ID, Vendor ID return a UR Note: This bit is still implemented as a RW/L bit, but is no longer used by the hardware to return UR as specified above.
8	0h	RW/1C/V	Synchronous SMI Status (SPI_SYNC_SS) Status indication that the SPI Flash Controller has asserted a synchronous SMI. Hardware clears the bit when it sends the De-assert Synchronous SMI message. 0: default state 1: SPI flash controller asserted Synchronous SMI
7	0h	RW/L	BIOS Interface Lock-Down (BILD) When set, prevents BBS and ASE_BWP from being changed. This bit can only be written from 0 to 1 once.
6	0h	RW/V/L	Boot BIOS Strap (BBS) This field determines the destination of accesses to the BIOS memory range. 0: SPI 1: Reserved The range that is decoded is further qualified by the BIOS Decode Enable (BDE) register. The initial value of this bit is determined by the BBS pinstrap. The value in this field can be overwritten by software as long as the BIOS Interface Lock-Down (BILD) is not set.
5	1h	RW/L	Enable InSMM.STS (EISS) When this bit is set, the BIOS region is not writable until in SMM mode. If this bit [5] is set, then WPD must be a '1' and the CPU must be in SMM mode in order to write to BIOS regions of SPI Flash. If this bit [5] is clear, then SMM mode is a don't care. This bit is locked by LE (bit 1 of this register).
4	0h	RO/V	Top Swap Status (TSS) This bit provides a read-only path to view the state of the Top Swap bit. It is duplicated here to be consistent with the eSPI version of the BC register.
3:2	2h	RW	SPI Read Configuration (SRC) These bits are located in PCI Config space to allow them to be set early in the boot flow. This 2-bit field controls two policies related to BIOS reads on the SPI interface: Bit 3 - Prefetch Enable Bit 2 - Cache Disable Settings are summarized below: Bits [3:2]: 00: No prefetching, but caching enabled. Direct Memory reads load the read buffer cache with 'valid' data, allowing repeated reads to the same range to complete quickly. 01: No prefetching and no caching. One-to-one correspondence of host BIOS reads to SPI cycles. This value can be used to invalidate the cache. 10: Prefetching and Caching enabled. This mode is used for long sequences of short reads to consecutive addresses (i.e. shadowing). 11: Reserved (not allowed). Caching must be enabled when Prefetching is enabled. This eliminates the need for a complex prefetch-flushing mechanism
1	0h	RW/L	Lock Enable (LE) When set, setting the WPD bit will cause a synchronous SMI. When cleared, setting the WPD bit will not cause SMI. Once set, this bit can only be cleared by a PLTRST#. When this bit is set, EISS - bit [5] of this register is locked down.
0	0h	RW	Write Protect Disable (WPD) When set, access to the BIOS space is enabled for both read and write cycles to BIOS. When cleared, only read cycles are permitted to the SPI flash. When this bit is written from a '0' to a '1' and the LE bit is also set, a synchronous SMI is generated. This ensures that only SMM code can update BIOS.