BIOS Control (ESPI_BC) – Offset dc - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

BIOS Control (ESPI_BC) – Offset dc

Bit Range	Default	Access	Field Name and Description
31:12	0h	RO	Reserved (RSVD_1) Reserved
11	0h	RW/L	BIOS Write Reporting (Async-SMI) Enable (BWRE) 1'b0: Disable reporting of BIOS Write event. 1'b1: Enable reporting of BIOS Write event (PCBC.BWRS = 1) using Async-SMI.
10	0h	RW/1C/V	BIOS Write Status (BWRS) HW sets this bit if a memory write access is detected to a protected BIOS range. 1'b0: Memory write to BIOS region not attempted or attempted with PCBC.WPD = 1. 1'b1: A memory write transaction to BIOS region has been received with PCBC.WPD = 0. Note: An Async-SMI message is generated to report this event if PCBC.BWRE is set. SW must write a 1 to this bit to clear it, which will also deassert the Async-SMI, if PCBC.BWRE is set.
9	0h	RO	Reserved (RSVD_2) Reserved
8	0h	RW/1C/V	BIOS Write Protect Disable Status (BWPDS) HW sets this bit if configuration write access is detected to protected PCBC.WPD bit. 1'b0: No attempt has been made to set PCBC.WPD with PCBC.LE = 1. 1'b1: A configuration write request has been received to set PCBC.WPD (0 1) with PCBC.LE = 1. An IOSF-SB Sync-SMI (Assert_SSMI) message is generated to report this event if HW sets this bit. The unsuccessful completion for the configuration write is returned upon receiving the SMI_Ack message response. SW must write a 1 to this bit to clear it, which will also deassert the Sync-SMI (IOSF-SB Deassert_SSMI message is generated). The Sync-SMI sets the PMC SMI_STS.TCO_STS register.
7	0h	RW/L	BIOS Interface Lock-Down (BILD) When set, prevents BC.TS and BC.BBS from being changed. This bit can only be written from 0 to 1 once. BIOS Note: This bit is not backed up in the RTC well. This bit should also be set in the BUC register in the RTC device to record the last state of this value following a cold reset.
6	0h	RW/V/L	Boot BIOS Strap (BBS) This field determines the destination of accesses to the BIOS memory range. For the default, Functional Strap section of Signal Description chapter for details. Bits Description 0: SPI 1: Reserved The range that is decoded is further qualified by other configuration bits described in the respective sections. The value in this field can be overwritten by software as long as the BIOS Interface Lock-Down is not set.
5	1h	RW/L	Enable InSMM.STS (EISS) When this bit is set, the BIOS region is not writable until SMM sets the InSMM.STS bit. Today BIOS Flash is writable if WPD is a 1. If this bit (5) is set, then WPD must be a 1 and InSMM.STS (0xFED3_0880(0)) must be 1 also. If this bit (5) is clear, then BIOS is writable based only on WPD = 1 and the InSMM.STS is a dont care.
4	0h	RO/V	Top Swap (TS) When set, the PCH will invert either A16, A17, or A18 for cycles going to the BIOS space (but not the Feature space). When cleared, the PCH will not invert A16. If booting from eSPI, then the Boot Block Size is fixed at 64KB and A16 is inverted if Top Swap is enabled. If booting from SPI, then the BOOT_BLOCK_SIZE soft strap determines if A16, A17, or A18 should be inverted if Top Swap is enabled. Note: If the Top-Swap strap is asserted, then this bit cannot be cleared by software. The strap jumper should be removed and the system rebooted. BIOS Note: This bit provides a read-only path to view the state of the Top Swap strap. It is backed up and driven from the RTC well. BIOS will need to program the corresponding register in the RTC well, which will be reflected in this register.
3	0h	RO	Reserved (RSVD) Reserved
2	0h	RO/V	eSPI Enable Pin Strap (ESPI) eSPI Enable Pin Strap (ESPI): This field determines the destination of accesses to the D31:F0 and related Fixed and Variable IO and Memory decode ranges, including BIOS memory range. 1'b0: Reserved 1'b1: eSPI is the D31:F0 target. This field cannot be overwritten by software (unlike the PCBC.BBS field). Note: While this register is reset on PLTRST# assertion, eSPI uses its internal copy, which is reset on eSPI_Reset# (== RSMRST#), for all operations.
1	0h	RW/L	Lock Enable (LE) When set, setting the WP bit will cause SMI. When cleared, setting the WP bit will not cause SMI. Once set, this bit can only be cleared by a PLTRST#. When this bit is set, EISS - bit (5) of this register is locked down.
0	0h	RW	Write Protect Disable (WPD) When set, access to the BIOS space is enabled for both read and write cycles to BIOS. When cleared, only read cycles are permitted to the FWH or SPI flash. When this bit is written from a 0 to a 1 and the LE bit is also set, an SMI# is generated. This ensures that only SMM code can update BIOS.