Clock Gating (XHCLKGTEN) – Offset 50 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Clock Gating (XHCLKGTEN) – Offset 50

Bit Range	Default	Access	Field Name and Description
31	0h	RW	Enable Frame Clk Gating When Active Periodic EPs On Scheduler (PRDCEP_FRCLK_GATEEN) Enable Frame Clk Gating When Active Periodic EPs On Scheduler
30	0h	RW	Extend EU3S To U2 (EXTD_EU3S_TO_U2) Extend EU3S To U2 to gate frame_clk
29	0h	RO	Reserved
28	0h	RW	Nak'ing USB2.0 EPs for Backbone Clock Gating and PLL Shutdown (NUEFBCGPS) This field controls whether Naking USB2.0 EPs, once in Naking low priority schedule, should be considered as active for the considerations for backbone clock gating and PLL shutdown or not. 0: Naking USB2.0 EPs are not considered to be active for Backbone Clock Gating and PLL Shutdown evaluation. 1: Naking USB2.0 EPs are considered to be active for Backbone clock gating and PLL shutdown evaluation.
27	1h	RW	SRAM Power Gate Enable (SRAMPGTEN) This register enables the SRAM Power Gating when PLL shutdown conditions for all clock domains have been met 0 - Disallow SRAM Power Gating. 1 - Allow SRAM Power Gating
26	1h	RW	SS Link PLL Shutdown Enable (SSLSE) This register enables the SS P3 state to be exposed to PXP PLL Shutdown conditions on behalf of all USB SS Ports ontop of trunk clock gating. 0 - P3 state NOT allowed to result in PXP PLL shutdown. 1- P3 state allowed to result in PXP PLL shutdown
25	1h	RW	USB2 PLL Shutdown Enable (USB2PLLSE) When set, this bit allows USB2 PLL to be shutdown when HS Link trunk clock is gated, and xHC can tolerate PLL spin up time for subsequent clock request.
24	1h	RW	IOSF Sideband Trunk Clock Gating Enable (IOSFSTCGE) When set, this bit allows the IOSF sideband clock trunk to be gated when idle conditions are met.
23:20	dh	RW	HS Backbone PXP Trunk Clock Gate Enable (HSTCGE) This register determines the HS Ux state(s) which will be exposed to Backbone PXP trunk gating of core clock. Uy is a state allowed to result in trunk gating when ss_tcg_ux_en(x) is asserted. (0) ==) U0 or deeper (1) ==) NA (no support for U1) (2) ==) U2 (L1) or deeper (3) ==) U3 (L2) or deeper
19:16	fh	RW	SS Backbone PXP Trunk Clock Gate Enable (SSTCGE) This register determines the SS Ux state(s) which will be exposed to Backbone PXP trunk gating of core clock. Uy is a state allowed to result in trunk gating when ss_tcg_ux_en(x) is asserted. (0) ==) U0 or deeper (1) ==) U1 or deeper (2) ==) U2 or deeper (3) ==) U3 or deeper
15	0h	RW	XHC Ignore_EU3S (XHCIGEU3S) This register determines if the xHC will use the EU3S as a condition to allow for Frame timer gating. 0 - xHC may allow frame timer to be gated when EU3S is set and all ports are in the required state. 1 - xHC may allow frame timer to be gated regardless of EU3S.
14	1h	RW	XHC Frame Timer Clock Shutdown Enable (XHCFTCLKSE) This register determines if the xHC will allow the frame timer clock to be gated. 0 - xHC will not allow ICC PLL 96MHz output to be shutdown thus keeping the frame timer running. 1 - xHC will allow ICC PLL 96MHz output to be shutdown under specific conditions.
13	1h	RW	XHC Backbone PXP Trunk Clock Gate In Presence of ISOCH EP (XHCBBTCGIPISO) This register controls the policy on allowing Backbone PXP trunk clock gate in the presence of IDLE ISOCH EPs with active DB. Allows the periodic active to be used in enabling Backbone PXP trunk clock gating of core clock. 0 - Trunk gate of core clock is not allowed when ISOCH EP DB is set and ISOCH EPs are idle. 1 - Allow trunk gate of core clock when ISOCH EP DB is set and ISOCH EPs are idle.
12	0h	RW	XHC HS Backbone PXP Trunk Clock Gate U2 non RWE (XHCHSTCGU2NRWE) This register controls the policy on allowing Backbone PXP trunk gating of core clock when there is atleast 1 non Remote Wake Enabled HS Port in U2. 0 - Prevent trunk gate of core clock when a non RWE HS Port is in U2. 1 - Allow trunk gate of core clock when a non RWE HS Port is in U2.
11:10	3h	RW	XHC USB2 PLL Shutdown Lx Enable (XHCUSB2PLLSDLE) This register determines the HS Link state(s) which will be exposed to USB2 PLL Shutdown conditions on behalf of all USB2 HS Ports. Ly is a state allowed to result in USB2 PLL Shutdown when en(x) is asserted. 0 = L1 or deeper 1 = L2 or deeper
9:8	1h	RW	HS Backbone PXP PLL Shutdown Ux Enable (HSUXDMIPLLSE) This register determines the Ux state(s) which will be exposed to PXP PLL Shutdown conditions. PLL Shutdown is allowed in: 00b: Disabled (Link states shall be disabled for DMI PLL shutdown) 01b: U0 or conditions for 10b setting. 10b: U2 or conditions for 11b setting. 10b: U3, Disconnected, Disabled or Powered-Off.
7:5	1h	RW	SS Backbone PXP PLL Shutdown Ux Enable (SSPLLSUE) This register determines the Ux state(s) which will be exposed to DMI PLL Shutdown conditions. PLL Shutdown is allowed in: 000b: Disabled (Link states shall be ignored for DMI PLL shutdown). 001b: U0 or conditions for 010b setting 010b: U1 or conditions for 011b setting 011b: U2 or conditions for 100b setting 100b: U3, Disconnected, Disabled or Powered-Off
4	1h	RW	XHC Backbone Local Clock Gating Enable (XHCBLCGE) When set, this bit allows XHCI Controller IP backbone clock to be locally gated when idle conditions are met.
3	1h	RW	HS Link Trunk Clock Gating Enable (HSLTCGE) When set, this bit allows High Speed Link control's 480 MHz and its 48/60 MHz link clock trunk to be gated when idle conditions are met.
2	1h	RW	SS Link Trunk Clock Gating Enable (SSLTCGE) When set, this bit allows the SuperSpeed Link control's 250 MHz and its divided 125 MHz link clock trunk to ge gated when idle conditions are met.
1	1h	RW	IOSF Backbone Trunk Clock Gating Enable (IOSFBTCGE) When set, this bit allows the IOSF backbone clock trunk to be gated when idle conditions are met.
0	1h	RW	IOSF Gasket Backbone Local Clock Gating Enable (IOSFBLCGE) When set, this bit allows the IOSF Gasket backbone clock to be locally gated when idle conditions are met.

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Clock Gating (XHCLKGTEN) – Offset 50