Control 0 (SSCR0) – Offset 0 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Control 0 (SSCR0) – Offset 0

The Enhanced SSP Control 0 registers contain twelve different bit fields that control various functions within the Enhanced SSP. All bits must be set to the preferred value before enabling the Enhanced SSP. Note that Writes to reserved bits must be zeroes, and Read values of these bits is undetermined.

Bit Range	Default	Access	Field Name and Description
31	0h	RW	MOD (MOD) 0 = Normal SSP Mode : Full Duplex Serial peripheral interface. 1 = Reserved
30	0h	RW	ACS (ACS) 0 = for Clock selection which is determined by the NCS and ECS bits in this register. 1 = reserved
29	0h	RO	Reserved
28:24	0h	NA	RSVD0 (RSVD0) Reserved
23	0h	RW	TIM (TIM) Transmit FIFO Under Run Interrupt Mask When set, this bit will mask the Transmit FIFO Under Run (TUR) event from generating an SSP interrupt. The SSSR status register will still indicate that an TUR event has occurred. This bit can be written to at any time (before or after SSP is enabled). 0 = Transmit FIFO Under Run(TUR) events will generate an SSP interrupt 1 = TUR events will be masked
22	0h	RW	RIM (RIM) Receive FIFO Over Run Interrupt Mask When set, this bit will mask the Receive FIFO Over Run (ROR) event from generating an SSP interrupt. The SSSR status register will still indicate that an ROR event has occurred. This bit can be written to at any time (before or after SSP is enabled) 0 = Receive FIFO Over Run(ROR) events will generate an SSP interrupt 1 = ROR events will be masked
21	0h	RW	NCS (NCS) Network Clock Select The SSCR0.NCS bit in conjunction with SSCR0.ECS determines which clock is used. 0 = Clock selection is determined by ECS bit 1 = Reserved
20	0h	RW	EDSS (EDSS) Extended Data Size Select The 1-bit extended field is used in conjunction with the data size select SSCR0.DSS bits to select the size of the data transmitted and received by the Enhanced SSP. 0 - A zero is prepended to the DSS value which sets the DSS range from 4 -16 bits 1 - A one is pre-appended to the DSS value which sets the DSS range from 17-32 bits
19:8	0h	RW	SCR (SCR) Serial Clock Rate Value used to generate transmission rate of SSP. Note: The SPI Interface Controller (SSP) baud rate (or Serial bit-rate clock SPI_CLK_OUT) can be generated either by the M/N divider or internally to the SSP (SSCR0.SCR) by dividing the on-chip SSP_CLK (output of M/N) to generate baud rates.
7	0h	RW	SSE (SSE) Synchronous Serial Port Enable The SSP enable bit, SSCR0.SSE, enables and disables all SSP operations. When SSCR0.SSE=0, the Enhanced SSP is disabled; when SSCR0.SSE=1, it is enabled. When the Enhanced SSP is disabled, all of its clocks can be stopped by programmers to minimize power consumption. On reset, the Enhanced SSP is disabled. When the SSCR0.SSE bit is cleared during active operation, the Enhanced SSP is disabled immediately, terminating the current frame being transmitted or received. Clearing SSCR0.SSE resets the Enhanced SSP FIFOs and the Enhanced SSP status bits; however, the Enhanced SSP Control registers are not reset. Note: After reset or after clearing the SSCR0.SSE, users must ensure that the SSCR1, SSITR and SSTO control registers are properly re-configured and that the SSSR register is reset before re- enabling the Enhanced SSP with the SSCR0.SSE. Also, the SSCR0.SSE bit must be cleared before reconfiguring the SSCR0, SSCR1, registers; other control bits in SSCR0 can be written at the same time as the SSCR0.SSE. When any SSP is disabled, its five pins can be used as GPIOs. 0 = SSP operation disabled 1 = SSP operation enabled.
6	0h	RW	ECS (ECS) External Clock Select: 0 = use On-chip clock (output of M/N Divider) to produce the SSP's serial clock (SSPSCLK). Selects the use of the the output of the M/N Divider (MBAR0 + 0x800, CLOCK_PARAMS) to create the SSP's serial clock (SSPCLK) Note: Setting M=N=1 will provide a pass through of the M/N Divider of the serial clock. See SCR for Serial Clock Rate generation. Note: The input (SSPEXTCLK) is treated as SSPSCLKEN, a clock enable used to gate the SSPSCLK output. When the external signal SSPSCLKEN changes, there will be a 1 -2 clock lag before the SSPSCLK is started or stopped due to the internal synchronization of this signal. 1 = Reserved
5:4	0h	RW	FRF (FRF) Frame Format Set to 00 - Motorola Serial Peripheral Interface (SPI) 01 = reserved 10 = reserved 11 = reserved
3:0	0h	RW	DSS (DSS) Data Size Select With EDSS as MSB. The CPU or DMA access data through the Enhanced SSP Ports Transmit and Receive FIFOs. A CPU access takes the form of programmed I/O, transferring one FIFO entry per access. CPU accesses would normally be triggered off of an SSSR Interrupt and must always be 32 bits wide. CPU Writes to the FIFOs are 32 bits wide, but the serializing logic will ignore all bits beyond the programmed FIFO data size (EDSS/DSS value). CPU Reads to the FIFOs are also 32 bits wide, but the Receive data written into the RX FIFO (from the RXD line) is stored with zeroes in the MSBs down to the programmed data size. The FIFOs can also be accessed by DMA Single transactions, which must be 1, 2 or 4 bytes, depending upon the EDSS value, and must also transfer one FIFO entry per access. When the SSCR0.EDSS bit is set, DMA Single transactions must be 4 bytes (the DMA must have the Enhanced SSP configured as a 32-bit peripheral).The DMAs _TR.width register must be at least the SSP data size programmed into the SSP control registers EDSS and DSS. The FIFO is seen as one 32-bit location by the processor. For Writes, the Enhanced SSP port takes the data from the Transmit FIFO, serializes it, and sends it over the serial wire (SSPTXD) to the external peripheral. Receive data from the external peripheral (on SSPRXD) is converted to parallel words and stored in the Receive FIFO. A programmable FIFO trigger threshold, when exceeded, generates an Interrupt or DMA service request that, if enabled, signals the CPU or DMA respectively to empty the Receive FIFO or to refill the Transmit FIFO. The Transmit and Receive FIFOs are differentiated by whether the access is a Read or a Write transfer. Reads automatically target the Receive FIFO, while Writes will write data to the Transmit FIFO. From a memory-map perspective, they are at the same address. FIFOs are 64 samples deep by 32 bits wide. Each read or write is to 1 SSP sample. The 4-bit Data Size Select SSCR0.DSS field is used in conjunction with the extended data size select SSCR0.EDSS bit to select the size of the data transmitted and received by the Enhanced SSP. The concatenated 5-bit value of SSCR0.EDSS and SSCR0.DSS provides a data range from 4 to 32 bits in length. Note: When data is programmed to be less than 32 bits, the FIFO should be programmed right-justified. Although it is possible to program data sizes of 1, 2, and 3 bits, these sizes are reserved and produce unpredictable results in the Enhanced SSP. 0011 4 bits 0111 8 bits 1111 16, 32 bits ( Note: To differentiate between 16 bits and 32 bits check the EDSS bit, for 32 bit data EDSS = 1)