Control 1 (SSCR1) – Offset 4 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Control 1 (SSCR1) – Offset 4

The Enhanced SSP Control 1 registers contain bit fields that control various SSP functions. Bits must be set to the preferred value before enabling the Enhanced SSP. Note that Writes to reserved bits should be zeroes, and Read value of these bits are undetermined.

Bit Range	Default	Access	Field Name and Description
31:24	0h	RO	Reserved
23	0h	RW	Receive With Out Transmit (RWOT) Receive With Out Transmit The SSCR1.RWOT bit is a read-write bit used to put the Enhanced SSP into a mode similar to half duplex. When the Enhanced SSP is in Transmit/Receive mode as determined SSCR1.RWOT=0, the Enhanced SSP simultaneously transmits and receives data (as supported by the individual protocols, i.e., normally all modes are full duplex except microwire) and the serial clock SSPSCLK only toggles while an active data transfer is underway. When in Receive-without-Transmit mode as determined by SSCR1.RWOT=1, the Enhanced SSP will continue to clock in receive data despite data existing or not in the Transmit FIFO. Data is sent/received according to the selected format immediately after the Enhanced SSP enable bit (SSCR0.SSE) is set.This allows the Enhanced SSP to receive data without transmitting data (half-duplex only). During this mode, if there is no data to send, programmers should disable the DMA service requests and Interrupts for the Transmit FIFO (clear the SSCR1.TSRE and SSCR1.TIE bits). If the Transmit FIFO is empty, the SSPTXD line will be driven to 0. The Transmit FIFO underrun condition will not occur when SSCR1.RWOT=1. When RWOT is enabled, the SSSR.BUSY bit will remain active (set to 1) until software clears the RWOT bit. If the Enhanced SSP has been in RWOT mode, and software disables this by clearing the RWOT bit, an extra frame cycle may occur due to the synchronization between clock domains. This bit must not be used when the SSCR0.MOD bit is set. 0 - Transmit/Receive mode 1 - Receive without transmit mode Warning: When RWOT =1, the first entry of the TX FIFO must be initialized with all zeros. Note: RWOT is not used in Windows drivers at all. When you enable RWOT you have no control on the data flow (the clock is free-running). Even if we have half-duplex operation support from windows we need to control how many data we need to read without transmit. We use full-duplex operation to do that putting dummy data into the TX FIFO. Registers SIRFL, TX_BIT_COUNT and RX_BIT_COUNT cannot be referred when using RWOT mode.
22	0h	RW	TRAIL (TRAIL) 0 = Processor based, trailing bytes are handled by processor 1 = DMA based, trailing bytes are handled by DMA
21	0h	RW	Transmit FIFO Service Request Enable (TSRE) Transmit FIFO Service Request Enable The SSCR1.TSRE bit enables the Transmit FIFO DMA Service Request. When SSCR1.TSRE=0, the DMA Service Request is masked, and the state of the transmit FIFO service request (SSSR.TFS) bit within the Enhanced SSP Status register is ignored. When SSCR1.TSRE=1, the DMA Service Request is enabled, and whenever SSSR.TFS is set to one, a DMA Service Request is made to the DMA. Note that programming SSCR1.TSRE=0 does not affect the current state of SSSR.TFS or the ability of the Transmit FIFO logic to set and clear SSSR.TFS it only blocks the generation of the DMA Service Request. Also, the state of SSCR1.TSRE does not affect the generation of the Interrupt, which is asserted whenever the SSSR.TFS is set to 1.
20	0h	RW	Receive FIFO Service Request Enable (RSRE) Receive FIFO Service Request Enable The SSCR1.RSRE bit enables the Receive FIFO DMA Service Request. When SSCR1.RSRE=0, the DMA Service Request is masked, and the state of the receive FIFO service request SSSR.RFS bit within the Enhanced SSP Status register is ignored. When SSCR1.RSRE=1, the DMA Service Request is enabled, and whenever SSSR.RFS is set to one, a DMA Service Request is made to the DMA. Note that programming SSCR1.RSRE=0 does not affect the current state of SSSR.RFS or the ability of the Receive FIFO logic to set and clear SSSR.RFS it only blocks the generation of the DMA Service Request. Also, the state of SSCR1.RFRS does not affect the generation of the Interrupt, which is asserted whenever the SSSR.RFS is set to 1. 0 = DMA Service Request is disabled 1 = DMA Service Request is enabled
19	0h	RW	Receive FIFO Time-out Interrupt Enable (TINTE) Receive FIFO Time-out Interrupt Enable The SSCR1.TINTE is a read-write bit used to mask or enable the Receiver Time-out Interrupt. When SSCR1.TINTE=0, the Interrupt is masked and the state of the SSSR.TINT bit is ignored by the Interrupt controller. When SSCR1.TINTE=1, the Interrupt is enabled, and whenever the SSSR.TINT bit is set to one an Interrupt request is made to the Interrupt controller. Note that programming SSCR1.TINTE=0 does not affect the current state of the SSSR.TINT or the ability of logic to set and clear the SSSR.TINT; it only blocks the generation of the Interrupt request. 0 = Receiver Time-out interrupts are disabled 1 = Receiver Time-out interrupts are enabled
18	0h	RO	Reserved
17	0h	NA	RSVD1 (RSVD1) Reserved
16	0h	RW	IFS (IFS) Invert Frame Signal 0 - Frame signal (Chip Select) is active low 1 - Frame signal (Chip Select) is active high
15	0h	RO	Reserved
14	0h	RW	EFWR (EFWR) Enable FIFO Write/Read (test mode bit) This bit enables a Test mode for the Enhanced SSP. When SSCR1.EFWR = 0, the Enhanced SSP operates in the Normal mode described in this document. When SSCR1.EFWR = 1, the Enhanced SSP enters a mode that whenever the CPU reads or writes to the Enhanced SSP Data register, it actually reads and writes directly to either the Transmit FIFO or the Receive FIFO, depending on the programmed state of the select FIFO for enable FIFO write/read (SSCR1.STRF) bit. With SSCR1.STRF = 0, all Writes to the SSDR are performed on the Transmit FIFO, and Reads to the SSDR will read back the data written to the Transmit FIFO in first-in-first-out order. With SSCR1.STRF = 1, all Writes to the SSDR are performed on the Receive FIFO, and Reads to the SSDR will read back the data written to the Receive FIFO in first-in-firstout order. In EFWR Test mode, data will not be transmitted on the SSPTXD pin, data input on the SSPRXD pin will not be stored, and the busy and ROR bits will no t work. The Interrupt Test Register, however, will still be functional. Using software, this mode can test whether or not the Transmit FIFO or the Receive FIFO operates properly as a FIFO memory stack. Software should verify that the SSSR.CSS bit has gone from a 1 to a 0 before reading the TX FIFO. 0 = FIFO write/read special function is disabled (normal SSP operational mode) 1 = FIFO write/read special function is enabled.
13:5	0h	NA	Res_13_5 (Res_13_5) Reseved
4	0h	RW	Motorola SPI SSPSCLK Phase Setting (SPH) Motorola SPI SSPSCLK phase setting The SSCR1.SPH bit determines the phase relationship between the SSPSCLK and the serial frame (SSPSFRM) pins when the Motorola* SPI format is selected (SSCR0.FRF=00). When SSCR1.SPH=0, SSPSCLK remains in its Inactive/Idle state (as determined by the SSCR1.SPO setting) for one full cycle after SSPSFRM is asserted low at the beginning of a frame. SSPSCLK continues to transition for the rest of the frame and is then held in its Inactive state for one-half of an SSPSCLK period before SSPSFRM is de-asserted high at the end of the frame. When SSCR1.SPH=1, SSPSCLK remains in its Inactive/Idle state (as determined by the SSCR1.SPO setting) for one-half cycle after SSPSFRM is asserted low at the beginning of a frame. SSPSCLK continues to transition for the remainder of the frame, and is then held in its Inactive state for one full SSPSCLK period before SSPSFRM is de-asserted high at the end of the frame. The combination of the SSCR1.SPO and SSCR1.SPH settings determines when SSPSCLK is active during the assertion of SSPSFRM, and which SSPSCLK edge transmits and receives data on the SSPTXD and SSPRXD pins. When SSCR1.SPO and SSCR1.SPH are programmed to the same value (both 0 or both 1), Transmit data is driven on the falling edge of SSPSCLK, and Receive data is latched on the rising edge of SSPSCLK. When SSCR1.SPO and SSCR1.SPH are programmed to opposite values (one 0 and the other 1), Transmit data is driven on the rising edge of SSPSCLK, and Receive data is latched on the falling edge of SSPSCLK. 0 - SSPSCLK is inactive one cycle at the start of a frame and cycle at the end of a frame 1 - SSPSCLK is inactive for one halfcycle at the start of a frame and one cycle at the end of a frame
3	0h	RW	SPO (SPO) Motorola SPI SSPSCLK polarity setting The SSCR1.SPO bit selects the polarity of the inactive state of the SSPSCLK pin when the Motorola* SPI format is selected (SSCR0.FRF=00). For S SCR1.SPO=0, the SSPSCLK is held low in the Inactive or Idle state when the Enhanced SSP is not transmitting/receiving data. For SSCR1.SPO=1, the SSPSCLK is held high during the Inactive/Idle state. The programmed setting of the SSCR1.SPO alone does not determine which SSPSCLK edge transmits or receives data the SSCR1.SPO setting in combination with the SSPSCLK phase bit SSCR1.SPH does. 0 - The inactive or idle state of SSPSCLK is low 1 - The inactive or idle state of SSPSCLK is high
2	0h	RO	Reserved
1	0h	RW	Transmit FIFO Interrupt Enable (TIE) Transmit FIFO Interrupt Enable The SSCR1.TIE bit enables the Transmit FIFO Service Request Interrupt. When SSCR1.TIE=0, the Interrupt is masked, and the state of the transmit FIFO service request (SSSR.TFS) bit within the Enhanced SSP Status register is ignored. When SSCR1.TIE=1, the Interrupt is enabled, and whenever SSSR.TFS is set to one, an Interrupt request is made to the Interrupt controller. Note that programming SSCR1.TIE=0 does not affect the current state of SSSR.TFS or the ability of the Transmit FIFO logic to set and clear SSSR.TFS it only blocks the generation of the Interrupt request. Also, the state of SSCR1.TIE does not affect the generation of the Transmit FIFO DMA service request, which is asserted whenever the SSSR.TFS is set to 1. 0 - Transmit FIFO level interrupt is disabled 1 - Transmit FIFO level interrupt is enabled
0	0h	RW	Transmit FIFO Interrupt Enable (RIE) Receive FIFO Interrupt Enable The SSCR1.RIE bit enables the Receive FIFO Service Request Interrupt. When SSCR1.RIE=0, the Interrupt is masked, and the state of the receive FIFO service request SSSR.RFS bit within the Enhanced SSP Status register is ignored. When SSCR1.RIE=1, the Interrupt is enabled, and whenever SSSR.RFS is set to one, an Interrupt request is made to the Interrupt controller. Note that programming SSCR1.RIE=0 does not affect the current state of SSSR.RFS or the ability of the Receive FIFO logic to set and clear SSSR.RFS it only blocks the generation of the Interrupt request. Also, the state of SSCR1.RIE does not affect the generation of the Receive FIFO DMA service request, which is asserted whenever the SSSR.RFS bit is set to 1. 0 - Receive FIFO level interrupt is disabled 1 - Receive FIFO level interrupt is enabled