D0i3 Control For HOST (IPC_d0i3C_HOST) – Offset 6d0 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

D0i3 Control For HOST (IPC_d0i3C_HOST) – Offset 6d0

This register is will be used for D0i3 SW flow. The description below also includes the type of access expected for the ISH FW for each configuration bit: 1. The Restore Required (RR) bit (bit [3]) should be RW for the ISH FW which can determine when to set and/or clear these bits depending on when the ISH FW determines whether restore is required although for ISH restore is never required since the power is never lost. 2. The D0i3 (i3) bit (bit [2]) should be RO for ISH FW as it needs to be written only by host SW. The ISH FW can determine to go to a low power state based on this bit. 3. The Interrupt Required (IR) bit (bit [1]) can be RO register for ISH FW and ISH FW can send an interrupt to Host by writing to the ish2host IPC doorbell register when this bit is set by SW. 4. The Command in Progress (CIP) register bit (bit [0]) is HW set and need to be cleared by ISH FW (Write 1 to clear?). A simple edge detect logic as shown in Figure 1 can be used for the setting of this bit in HW. The CIP register bit will be tied to a RTE entry in the IOAPIC as an interrupt source. Hence ISH FW will get an interrupt when the In addition to the registers, the IOSF2OCP Bridge should be parameterized for the following: 1. The device idle capability parameter (ENABLE_PCI_IDLE_CAP) need to be connected to a soft strap for ISH with a value of 1. 2. The STRAP for the MMIO address (strap_d0i3_offset) of D0i3 register (IPC offset address: h6D0) and the d0i3 valid (strap_d0i3_valid) bit needs should be appropriately tied. 3. The PCE register is made RO register by setting the appropriate parameter (Bridge top level strap: set_device_pg_config_type[5:0] is set to all 0s). This registers reset and clock domain will be in the OCP domain.

Bit Range	Default	Access	Field Name and Description
31:5	0h	RO	(RESERVED0) Reserved.
4	0h	RO	Interrupt Request Capable (IRC) Set to 1 by HW if it is capable of generating an interrupt on command completion, else 0. For ISH this bit will be tied to 0.
3	1h	RW/1C	Restore Required (RR) When set (by HW), SW must restore state to the IP. The state may have been lost due to a reset or full power lost. SW clears the bit by writing a 1. This bit will be set on initial power up.
2	0h	RW	D0i3 State (D0i3) SW sets this bit to 1 to move the IP into the D0i3 state. Writing this bit to 0 will return the IP to the fully active D0 state (D0i0).
1	0h	RW	Interrupt Required (IR) SW sets this bit to 1 to ask for an interrupt to be generated on completion of the command. SW must clear or set this on each write to this register.
0	0h	RO	Command In Progress (CIP) HW sets this bit on a 1->0 or 0->1 transition of bit [2]. While set, the other bits in this register are not valid and it is illegal for SW to write to any bit in this register. When clear all the other bits in the register are valid and SW may write to any bit.