Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2
ID | Date | Version | Classification |
---|---|---|---|
834576 | 10/10/2024 | 001 | Public |
DAP USB 2.0 Port <N> Control 1 (DAP_USB2_PORT_CONTROL_1_REG_0_MMIO) – Offset 89c8
Control and status registers for all DRD USB2 links.
All bits in this register must be in the Always ON Power domain (un-gated SUS or AON as appropriate).
The register applies to individual port. The offset of each port is 0x89C8 + N*0x10.
For example:
Port 0 offset: 0x89C8
Port 1 offset: 0x89D8
Port 3 offset: 0x89E8
...
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:11 | 0h | RO | Reserved |
10:8 | 1h | RO | Connector Type (CONNECTOR_TYPE) Specifies type of connector associated with this port. |
7:2 | 0h | RO | Reserved |
1 | 0h | RW | HW VBus Enable (HW_VBUS_ENABLE) This field applies to Port 0 (0-based) only. |
0 | 0h | RW | HW ID Enable (HW_ID_ENABLE) This field applies to Port 0 (0-based) only. |