DAP USB 3.0 Port <N> Control 0 (DAP_ESS_PORT_CONTROL_0_REG_0_MMIO) – Offset 8ac4 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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USB MMIO
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xDCI MMIO Device
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xDCI PCI Configuration

DAP USB 3.0 Port <N> Control 0 (DAP_ESS_PORT_CONTROL_0_REG_0_MMIO) – Offset 8ac4

Control and status registers for all DRD eSS links.
All bits in this register must be in the Always ON Power domain (un-gated SUS or AON as appropriate).
The register applies to individual port. The offset of each port: 0x*8AC4 + N*0x10.
For example:
Port 0 offset: 0x8AC4
Port 1 offset: 0x8AD4
Port 2 offset: 0x8AE4
...

Bit Range	Default	Access	Field Name and Description
31:17	0h	RO	Reserved
16	0h	RW	Gen 1 PCLK Request (GEN1_PCLK_REQ) This field contributes to the support of Type C connector in a platform that includes FIA. In the flow that sequences MODPHY ownership from guest controller to either xHCI or xDCI, FIA requires GEN1 PCLK which may be provisioned through programming of this field. SW writes this field to 1 to un-gate GEN1 PCLK, or 0 to gate GEN1 PCLK.
15:14	0h	RO	Reserved
13:9	0h	RW	Tunnel Connect Type (TUNNEL_CONNECT_TYPE) 00000 : 10G x1 00001 : 10G x2 All other, reserved.
8	0h	RW	SW VBus (SW_VBUS) SW sets this bit to 1 to inform xDCI of VBus presence. SW clears this bit to 0 to inform xDCI of VBus absence. VBus present in addition to link port in device state will arm the xDCI to communicate through USB interface.
7:5	1h	RW	Connector Event (CONNECTOR_EVENT) Refer to the corresponding 'DAP USB2 Port N Control 0 (0 <= N <= 31)' register field.
4	0h	RW	USBX_TNL_MODE_EN (CFG_UX_TNL_MODE_EN) USBX_TNL_MODE_EN
3	0h	RO	Reserved
2	0h	RW	PORT ORIENTATION (PORT_ORIENTATION) PORT ORIENTATION: 0: Normal connection 1: Flipped connection For flipped connection, Muxing agent would write to this bit before enabling the Host connection through SPR.
1	0h	RW	FORCE X1 CONNECT (FORCE_X1_CONNECT) FORCE X1 CONNECT Will be set for DP + USB connection. XHCI controller would not initialize non Config lane.
0	0h	RO	Reserved

DAP USB 3.0 Port <N> Control 1 (DAP_ESS_PORT_CONTROL_1_REG_0_MMIO)

DAP USB 2.0 Port <N> Status (DAP_USB2_PORT_STATUS_REG_0_MMIO) DAP USB 3.0 Port <N> Control 1 (DAP_ESS_PORT_CONTROL_1_REG_0_MMIO)